The understanding of gate capacitance matching on achieving a high performance NC MOSFET with sufficient mobility

C. K. Chiang, P. Husan, Y. C. Lou, F. L. Li, E. R. Hsieh, C. H. Liu, Steve S. Chung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We develop experimental approaches to quantitatively extract the negative capacitance of MIM in a gate stacked NCFET. It was found that the NC effect is highly dependent on the grain and dipole behaviors with different annealing temperature. Also, to achieve a better design of high-performance NCFET, we explore not only the capacitance matching between ferroelectric HZO MIM and MOSFET but also how effective mobility is affected by HZO dipoles. For capacitance matching, we observe a 50x enhancement of overall gate capacitance triggered by NC effect, while, however, it adversely generated the degradation of the mobility. This mobility degradation is induced by the remote scattering from the ferroelectric HZO dipoles. Fortunately, if suitable polarization can be formed to align the HZO dipoles, the effects of remote scattering can be mitigated. From a trade-off between gate capacitance and the mobility, an NCFET with desirable performance can be achieved.

Original languageEnglish
Title of host publication2019 Silicon Nanoelectronics Workshop, SNW 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9784863487024
DOIs
Publication statusPublished - 2019 Jun
Event24th Silicon Nanoelectronics Workshop, SNW 2019 - Kyoto, Japan
Duration: 2019 Jun 92019 Jun 10

Publication series

Name2019 Silicon Nanoelectronics Workshop, SNW 2019

Conference

Conference24th Silicon Nanoelectronics Workshop, SNW 2019
CountryJapan
CityKyoto
Period19/6/919/6/10

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Electronic, Optical and Magnetic Materials

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    Chiang, C. K., Husan, P., Lou, Y. C., Li, F. L., Hsieh, E. R., Liu, C. H., & Chung, S. S. (2019). The understanding of gate capacitance matching on achieving a high performance NC MOSFET with sufficient mobility. In 2019 Silicon Nanoelectronics Workshop, SNW 2019 [8782951] (2019 Silicon Nanoelectronics Workshop, SNW 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/SNW.2019.8782951