The impacts of contact etch stop layer thickness and gate height on channel stress in strained N-metal oxide semiconductor field effect transistors

K. C. Lin, Ming-Jenq Twu, R. H. Deng, Chuan-Hsi Liu

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

The stress induced by strain in the channel of metal oxide semiconductor field effect transistors (MOSFET) is an effective method to boost the device performance. The geometric dimensions of spacer, gate height, and the contact etch stop layer (CESL) are important factors among the feasible booster. This study utilized the mismatch of the thermal expansion coefficients of stressors to simulate the process-induced stress in the N-MOSFET. Different temperatures are applied to different region of the device to generate the required strain. The analysis was performed by welldeveloped finite element package. The composite spacers with variant width of inserted silicon nitride (SiO2 /SiN/SiO2 , ONO) were proposed and their impacts on channel stress were compared. Two aspects of the impacts of those factors on the channel stress in the longitudinal direction for N-MOSFET with variant channel length were investigated. Firstly, the channel stresses of device without CESL for different gate heights were studied. Secondly, with stress applied to CESL and ONO spacers, the induced stresses in the channel were analyzed for long/short gate length. Two conclusions were drawn from the results of simulation. The N-MOSFET device without CESL shows that the stressed spacer alone generates compressive stress and the magnitude increases along with higher gate height. The channel stress becomes tensile for device with CESL and increases when the thickness of CESL and the height of gate increase, especially for device with shorter gate length. The gate height plays more significant role in inducing channel stress compared with the thickness of CESL. The channel stress can be used to quantify the mobility of electron/hole for strained MOSFET device. Therefore, with the guideline disclosed in this study, better device performance can be expected for N-MOSFET.

Original languageEnglish
Pages (from-to)2673-2679
Number of pages7
JournalJournal of Nanoscience and Nanotechnology
Volume15
Issue number4
DOIs
Publication statusPublished - 2015 Jan 1

Fingerprint

Semiconductors
MOSFET devices
metal oxide semiconductors
Oxides
field effect transistors
Metals
Equipment and Supplies
spacers
boosters
Silicon nitride
Compressive stress
Tensile stress
acceleration (physics)
tensile stress
Thermal expansion
silicon nitrides
Hot Temperature
Guidelines
Electrons
thermal expansion

Keywords

  • CESL (Contact Etch Stop Layer)
  • Channel stress
  • N-MOSFET
  • Spacer stressor

ASJC Scopus subject areas

  • Bioengineering
  • Chemistry(all)
  • Biomedical Engineering
  • Materials Science(all)
  • Condensed Matter Physics

Cite this

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title = "The impacts of contact etch stop layer thickness and gate height on channel stress in strained N-metal oxide semiconductor field effect transistors",
abstract = "The stress induced by strain in the channel of metal oxide semiconductor field effect transistors (MOSFET) is an effective method to boost the device performance. The geometric dimensions of spacer, gate height, and the contact etch stop layer (CESL) are important factors among the feasible booster. This study utilized the mismatch of the thermal expansion coefficients of stressors to simulate the process-induced stress in the N-MOSFET. Different temperatures are applied to different region of the device to generate the required strain. The analysis was performed by welldeveloped finite element package. The composite spacers with variant width of inserted silicon nitride (SiO2 /SiN/SiO2 , ONO) were proposed and their impacts on channel stress were compared. Two aspects of the impacts of those factors on the channel stress in the longitudinal direction for N-MOSFET with variant channel length were investigated. Firstly, the channel stresses of device without CESL for different gate heights were studied. Secondly, with stress applied to CESL and ONO spacers, the induced stresses in the channel were analyzed for long/short gate length. Two conclusions were drawn from the results of simulation. The N-MOSFET device without CESL shows that the stressed spacer alone generates compressive stress and the magnitude increases along with higher gate height. The channel stress becomes tensile for device with CESL and increases when the thickness of CESL and the height of gate increase, especially for device with shorter gate length. The gate height plays more significant role in inducing channel stress compared with the thickness of CESL. The channel stress can be used to quantify the mobility of electron/hole for strained MOSFET device. Therefore, with the guideline disclosed in this study, better device performance can be expected for N-MOSFET.",
keywords = "CESL (Contact Etch Stop Layer), Channel stress, N-MOSFET, Spacer stressor",
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year = "2015",
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T1 - The impacts of contact etch stop layer thickness and gate height on channel stress in strained N-metal oxide semiconductor field effect transistors

AU - Lin, K. C.

AU - Twu, Ming-Jenq

AU - Deng, R. H.

AU - Liu, Chuan-Hsi

PY - 2015/1/1

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N2 - The stress induced by strain in the channel of metal oxide semiconductor field effect transistors (MOSFET) is an effective method to boost the device performance. The geometric dimensions of spacer, gate height, and the contact etch stop layer (CESL) are important factors among the feasible booster. This study utilized the mismatch of the thermal expansion coefficients of stressors to simulate the process-induced stress in the N-MOSFET. Different temperatures are applied to different region of the device to generate the required strain. The analysis was performed by welldeveloped finite element package. The composite spacers with variant width of inserted silicon nitride (SiO2 /SiN/SiO2 , ONO) were proposed and their impacts on channel stress were compared. Two aspects of the impacts of those factors on the channel stress in the longitudinal direction for N-MOSFET with variant channel length were investigated. Firstly, the channel stresses of device without CESL for different gate heights were studied. Secondly, with stress applied to CESL and ONO spacers, the induced stresses in the channel were analyzed for long/short gate length. Two conclusions were drawn from the results of simulation. The N-MOSFET device without CESL shows that the stressed spacer alone generates compressive stress and the magnitude increases along with higher gate height. The channel stress becomes tensile for device with CESL and increases when the thickness of CESL and the height of gate increase, especially for device with shorter gate length. The gate height plays more significant role in inducing channel stress compared with the thickness of CESL. The channel stress can be used to quantify the mobility of electron/hole for strained MOSFET device. Therefore, with the guideline disclosed in this study, better device performance can be expected for N-MOSFET.

AB - The stress induced by strain in the channel of metal oxide semiconductor field effect transistors (MOSFET) is an effective method to boost the device performance. The geometric dimensions of spacer, gate height, and the contact etch stop layer (CESL) are important factors among the feasible booster. This study utilized the mismatch of the thermal expansion coefficients of stressors to simulate the process-induced stress in the N-MOSFET. Different temperatures are applied to different region of the device to generate the required strain. The analysis was performed by welldeveloped finite element package. The composite spacers with variant width of inserted silicon nitride (SiO2 /SiN/SiO2 , ONO) were proposed and their impacts on channel stress were compared. Two aspects of the impacts of those factors on the channel stress in the longitudinal direction for N-MOSFET with variant channel length were investigated. Firstly, the channel stresses of device without CESL for different gate heights were studied. Secondly, with stress applied to CESL and ONO spacers, the induced stresses in the channel were analyzed for long/short gate length. Two conclusions were drawn from the results of simulation. The N-MOSFET device without CESL shows that the stressed spacer alone generates compressive stress and the magnitude increases along with higher gate height. The channel stress becomes tensile for device with CESL and increases when the thickness of CESL and the height of gate increase, especially for device with shorter gate length. The gate height plays more significant role in inducing channel stress compared with the thickness of CESL. The channel stress can be used to quantify the mobility of electron/hole for strained MOSFET device. Therefore, with the guideline disclosed in this study, better device performance can be expected for N-MOSFET.

KW - CESL (Contact Etch Stop Layer)

KW - Channel stress

KW - N-MOSFET

KW - Spacer stressor

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