TY - GEN
T1 - The guideline on designing face-tunneling FET for large-scale-device applications in IoT
AU - Hsieh, E. R.
AU - Lee, J. W.
AU - Lee, M. H.
AU - Chung, Steve S.
N1 - Funding Information:
This research was partially supported by a grant (60403011) from National Natural Science Foundation of China, and grants (2003ABA012) and (20045006071-17) from Science & Technology Department, Hubei Province and the People's Municipal Government of Wuhan respectively, China. This research was also supported by the grants (RGC and FRG) from Hong Kong Baptist University.
Publisher Copyright:
© 2017 JSAP.
PY - 2017/12/29
Y1 - 2017/12/29
N2 - A thorough understanding on how to design and to manufacture a face-tunneling TFET (f-TFET) has been provided. By taking advantage of an area-tunneling, in comparison to conventional point-tunneling FET, f-TFET can be enhanced in its current. This work shows I0 of f-TFET with one-order magnitude In enhancement than that of point-TFET(control), and the longer the gate length is, the higher the becomes. However, from experimental results, S.S. of f-TFET is a little worse than that of control and shows strong dependency on temperature because of dominance of trap-assisted tunneling. To understand how traps affect Ion of f-TFET, the charge-pumping measurement is utilized to examine trap distributions in the tunneling region. The results show that the channel/source interfacial traps degrade the performance of f-TFET, however, with careful treatment of the epi-process of f-TFET, this device with face-tunneling shows great potential for future IoT applications.
AB - A thorough understanding on how to design and to manufacture a face-tunneling TFET (f-TFET) has been provided. By taking advantage of an area-tunneling, in comparison to conventional point-tunneling FET, f-TFET can be enhanced in its current. This work shows I0 of f-TFET with one-order magnitude In enhancement than that of point-TFET(control), and the longer the gate length is, the higher the becomes. However, from experimental results, S.S. of f-TFET is a little worse than that of control and shows strong dependency on temperature because of dominance of trap-assisted tunneling. To understand how traps affect Ion of f-TFET, the charge-pumping measurement is utilized to examine trap distributions in the tunneling region. The results show that the channel/source interfacial traps degrade the performance of f-TFET, however, with careful treatment of the epi-process of f-TFET, this device with face-tunneling shows great potential for future IoT applications.
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U2 - 10.23919/SNW.2017.8242268
DO - 10.23919/SNW.2017.8242268
M3 - Conference contribution
AN - SCOPUS:85051139834
T3 - 2017 Silicon Nanoelectronics Workshop, SNW 2017
SP - 3
EP - 4
BT - 2017 Silicon Nanoelectronics Workshop, SNW 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 22nd Silicon Nanoelectronics Workshop, SNW 2017
Y2 - 4 June 2017 through 5 June 2017
ER -