The guideline on designing face-tunneling FET for large-scale-device applications in IoT

E. R. Hsieh, J. W. Lee, M. H. Lee, Steve S. Chung

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    A thorough understanding on how to design and to manufacture a face-tunneling TFET (f-TFET) has been provided. By taking advantage of an area-tunneling, in comparison to conventional point-tunneling FET, f-TFET can be enhanced in its current. This work shows I0 of f-TFET with one-order magnitude In enhancement than that of point-TFET(control), and the longer the gate length is, the higher the becomes. However, from experimental results, S.S. of f-TFET is a little worse than that of control and shows strong dependency on temperature because of dominance of trap-assisted tunneling. To understand how traps affect Ion of f-TFET, the charge-pumping measurement is utilized to examine trap distributions in the tunneling region. The results show that the channel/source interfacial traps degrade the performance of f-TFET, however, with careful treatment of the epi-process of f-TFET, this device with face-tunneling shows great potential for future IoT applications.

    Original languageEnglish
    Title of host publication2017 Silicon Nanoelectronics Workshop, SNW 2017
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages3-4
    Number of pages2
    ISBN (Electronic)9784863486478
    DOIs
    Publication statusPublished - 2017 Dec 29
    Event22nd Silicon Nanoelectronics Workshop, SNW 2017 - Kyoto, Japan
    Duration: 2017 Jun 42017 Jun 5

    Publication series

    Name2017 Silicon Nanoelectronics Workshop, SNW 2017
    Volume2017-January

    Other

    Other22nd Silicon Nanoelectronics Workshop, SNW 2017
    CountryJapan
    CityKyoto
    Period2017/06/042017/06/05

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Electronic, Optical and Magnetic Materials

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