The guideline on designing a high performance nc mosfet by matching the gate capacitance and mobility enhancement

Y. C. Luo; F. L. Li; E. R. Hsieh; C. H. Liu; Steve S. Chung; T. P. Chen; S. A. Huang; T. J. Chen; Osbert Chenz

doi:10.1109/VLSI-TSA.2019.8804688

The guideline on designing a high performance nc mosfet by matching the gate capacitance and mobility enhancement

Y. C. Luo, F. L. Li, E. R. Hsieh, C. H. Liu, Steve S. Chung, T. P. Chen, S. A. Huang, T. J. Chen, Osbert Chenz

Department of Mechatronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper, to provide a guideline of designing a high-performance NCFET, we explored not only the capacitance matching between ferroelectric HZO MIM and MOSFET but also how effective mobility is affected by HZO dipoles. For capacitance matching, we observe a 50x enhancement of overall gate capacitance triggered by NC effect, while, however, it generated an adverse degradation of the mobility. This mobility degradation is induced by the remote scattering from the ferroelectric HZO dipoles. Fortunately, if suitable polarization can be formed to align the HZO dipoles, the effects of remote scattering can be mitigated. From a trade-off between gate capacitance and the mobility, an NCFET with desirable characteristics can be achieved. Besides, we showed that improved SS is possible when the derivative of the voltage across the ferroelectric MIM is negative and is corresponding to the release of energy from the ferroelectric MIM which boosts SS.

Original language	English
Title of host publication	2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728109428
DOIs	https://doi.org/10.1109/VLSI-TSA.2019.8804688
Publication status	Published - 2019 Apr
Event	2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019 - Hsinchu, Taiwan Duration: 2019 Apr 22 → 2019 Apr 25

Publication series

Name	2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019

Conference

Conference	2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019
Country/Territory	Taiwan
City	Hsinchu
Period	2019/04/22 → 2019/04/25

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

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10.1109/VLSI-TSA.2019.8804688

Cite this

Luo, Y. C., Li, F. L., Hsieh, E. R., Liu, C. H., Chung, S. S., Chen, T. P., Huang, S. A., Chen, T. J., & Chenz, O. (2019). The guideline on designing a high performance nc mosfet by matching the gate capacitance and mobility enhancement. In 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019 Article 8804688 (2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-TSA.2019.8804688

The guideline on designing a high performance nc mosfet by matching the gate capacitance and mobility enhancement. / Luo, Y. C.; Li, F. L.; Hsieh, E. R. et al.
2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8804688 (2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Luo, YC, Li, FL, Hsieh, ER, Liu, CH, Chung, SS, Chen, TP, Huang, SA, Chen, TJ & Chenz, O 2019, The guideline on designing a high performance nc mosfet by matching the gate capacitance and mobility enhancement. in 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019., 8804688, 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019, Institute of Electrical and Electronics Engineers Inc., 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019, Hsinchu, Taiwan, 2019/04/22. https://doi.org/10.1109/VLSI-TSA.2019.8804688

Luo YC, Li FL, Hsieh ER, Liu CH, Chung SS, Chen TP et al. The guideline on designing a high performance nc mosfet by matching the gate capacitance and mobility enhancement. In 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 8804688. (2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019). doi: 10.1109/VLSI-TSA.2019.8804688

Luo, Y. C. ; Li, F. L. ; Hsieh, E. R. et al. / The guideline on designing a high performance nc mosfet by matching the gate capacitance and mobility enhancement. 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019. Institute of Electrical and Electronics Engineers Inc., 2019. (2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019).

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abstract = "In this paper, to provide a guideline of designing a high-performance NCFET, we explored not only the capacitance matching between ferroelectric HZO MIM and MOSFET but also how effective mobility is affected by HZO dipoles. For capacitance matching, we observe a 50x enhancement of overall gate capacitance triggered by NC effect, while, however, it generated an adverse degradation of the mobility. This mobility degradation is induced by the remote scattering from the ferroelectric HZO dipoles. Fortunately, if suitable polarization can be formed to align the HZO dipoles, the effects of remote scattering can be mitigated. From a trade-off between gate capacitance and the mobility, an NCFET with desirable characteristics can be achieved. Besides, we showed that improved SS is possible when the derivative of the voltage across the ferroelectric MIM is negative and is corresponding to the release of energy from the ferroelectric MIM which boosts SS.",

author = "Luo, {Y. C.} and Li, {F. L.} and Hsieh, {E. R.} and Liu, {C. H.} and Chung, {Steve S.} and Chen, {T. P.} and Huang, {S. A.} and Chen, {T. J.} and Osbert Chenz",

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AU - Luo, Y. C.

AU - Li, F. L.

AU - Hsieh, E. R.

AU - Liu, C. H.

AU - Chung, Steve S.

AU - Chen, T. P.

AU - Huang, S. A.

AU - Chen, T. J.

AU - Chenz, Osbert

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N2 - In this paper, to provide a guideline of designing a high-performance NCFET, we explored not only the capacitance matching between ferroelectric HZO MIM and MOSFET but also how effective mobility is affected by HZO dipoles. For capacitance matching, we observe a 50x enhancement of overall gate capacitance triggered by NC effect, while, however, it generated an adverse degradation of the mobility. This mobility degradation is induced by the remote scattering from the ferroelectric HZO dipoles. Fortunately, if suitable polarization can be formed to align the HZO dipoles, the effects of remote scattering can be mitigated. From a trade-off between gate capacitance and the mobility, an NCFET with desirable characteristics can be achieved. Besides, we showed that improved SS is possible when the derivative of the voltage across the ferroelectric MIM is negative and is corresponding to the release of energy from the ferroelectric MIM which boosts SS.

AB - In this paper, to provide a guideline of designing a high-performance NCFET, we explored not only the capacitance matching between ferroelectric HZO MIM and MOSFET but also how effective mobility is affected by HZO dipoles. For capacitance matching, we observe a 50x enhancement of overall gate capacitance triggered by NC effect, while, however, it generated an adverse degradation of the mobility. This mobility degradation is induced by the remote scattering from the ferroelectric HZO dipoles. Fortunately, if suitable polarization can be formed to align the HZO dipoles, the effects of remote scattering can be mitigated. From a trade-off between gate capacitance and the mobility, an NCFET with desirable characteristics can be achieved. Besides, we showed that improved SS is possible when the derivative of the voltage across the ferroelectric MIM is negative and is corresponding to the release of energy from the ferroelectric MIM which boosts SS.

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BT - 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019

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The guideline on designing a high performance nc mosfet by matching the gate capacitance and mobility enhancement

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