The FPGA implementation of 128-bits AES algorithm based on four 32-bits parallel operation

Chi Wu Huang; Chi Jeng Chang; Mao Yuan Lin; Hung Yun Tai

doi:10.1109/ISDPE.2007.128

The FPGA implementation of 128-bits AES algorithm based on four 32-bits parallel operation

Chi Wu Huang^*, Chi Jeng Chang, Mao Yuan Lin, Hung Yun Tai

^*Corresponding author for this work

Department of Industrial Education

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

14 Citations (Scopus)

Abstract

A 32-bit AES implementation is proposed in small Xilinx FPGA Chip (Spartan-3 XC3S200). It uses 148 slices, 11 Block RAMs (BRAMs) and achieves a throughput of 647 Mega bits per second ( Mbps) at 278 MHz working frequency. It achieve 3 times improvement in throughput and 3.4 times increase to the best known similar design in throughput per area and 8% smaller in slices area. An 128-bit AES implementation in FPGA (Virtex-II XC2VP20) by parallel operations of four above 32-bit AES is also presented. Comparison to state-of-art AES cores indicates that the proposed folded designed achieves 4780 Mbps and 410 slices, which outperformed the most recent works by 200% in throughput and requires 20% less reconfigurable area, which results over 250% improvement in throughput/slice metric.

Original language	English
Title of host publication	Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007
Pages	462-464
Number of pages	3
DOIs	https://doi.org/10.1109/ISDPE.2007.128
Publication status	Published - 2007
Event	1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007 - Chengdu, China Duration: 2007 Nov 1 → 2007 Nov 3

Publication series

Name	Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007

Conference

Conference	1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007
Country/Territory	China
City	Chengdu
Period	2007/11/01 → 2007/11/03

ASJC Scopus subject areas

General Computer Science
Economics, Econometrics and Finance (miscellaneous)

Access to Document

10.1109/ISDPE.2007.128

Cite this

Huang, C. W., Chang, C. J., Lin, M. Y., & Tai, H. Y. (2007). The FPGA implementation of 128-bits AES algorithm based on four 32-bits parallel operation. In Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007 (pp. 462-464). Article 4402734 (Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007). https://doi.org/10.1109/ISDPE.2007.128

The FPGA implementation of 128-bits AES algorithm based on four 32-bits parallel operation. / Huang, Chi Wu; Chang, Chi Jeng; Lin, Mao Yuan et al.
Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007. 2007. p. 462-464 4402734 (Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Huang, CW, Chang, CJ, Lin, MY & Tai, HY 2007, The FPGA implementation of 128-bits AES algorithm based on four 32-bits parallel operation. in Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007., 4402734, Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007, pp. 462-464, 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007, Chengdu, China, 2007/11/01. https://doi.org/10.1109/ISDPE.2007.128

Huang CW, Chang CJ, Lin MY, Tai HY. The FPGA implementation of 128-bits AES algorithm based on four 32-bits parallel operation. In Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007. 2007. p. 462-464. 4402734. (Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007). doi: 10.1109/ISDPE.2007.128

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abstract = "A 32-bit AES implementation is proposed in small Xilinx FPGA Chip (Spartan-3 XC3S200). It uses 148 slices, 11 Block RAMs (BRAMs) and achieves a throughput of 647 Mega bits per second ( Mbps) at 278 MHz working frequency. It achieve 3 times improvement in throughput and 3.4 times increase to the best known similar design in throughput per area and 8% smaller in slices area. An 128-bit AES implementation in FPGA (Virtex-II XC2VP20) by parallel operations of four above 32-bit AES is also presented. Comparison to state-of-art AES cores indicates that the proposed folded designed achieves 4780 Mbps and 410 slices, which outperformed the most recent works by 200% in throughput and requires 20% less reconfigurable area, which results over 250% improvement in throughput/slice metric.",

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The FPGA implementation of 128-bits AES algorithm based on four 32-bits parallel operation

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