The FPGA implementation of 128-bits AES algorithm based on four 32-bits parallel operation

Chi-Wu Huang, Chi Jeng Chang, Mao Yuan Lin, Hung Yun Tai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

Abstract

A 32-bit AES implementation is proposed in small Xilinx FPGA Chip (Spartan-3 XC3S200). It uses 148 slices, 11 Block RAMs (BRAMs) and achieves a throughput of 647 Mega bits per second ( Mbps) at 278 MHz working frequency. It achieve 3 times improvement in throughput and 3.4 times increase to the best known similar design in throughput per area and 8% smaller in slices area. An 128-bit AES implementation in FPGA (Virtex-II XC2VP20) by parallel operations of four above 32-bit AES is also presented. Comparison to state-of-art AES cores indicates that the proposed folded designed achieves 4780 Mbps and 410 slices, which outperformed the most recent works by 200% in throughput and requires 20% less reconfigurable area, which results over 250% improvement in throughput/slice metric.

Original languageEnglish
Title of host publicationProceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007
Pages462-464
Number of pages3
DOIs
Publication statusPublished - 2007 Dec 1
Event1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007 - Chengdu, China
Duration: 2007 Nov 12007 Nov 3

Publication series

NameProceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007

Other

Other1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007
CountryChina
CityChengdu
Period07/11/107/11/3

Fingerprint

Field programmable gate arrays (FPGA)
Throughput
Random access storage

ASJC Scopus subject areas

  • Computer Science(all)
  • Economics, Econometrics and Finance (miscellaneous)

Cite this

Huang, C-W., Chang, C. J., Lin, M. Y., & Tai, H. Y. (2007). The FPGA implementation of 128-bits AES algorithm based on four 32-bits parallel operation. In Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007 (pp. 462-464). [4402734] (Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007). https://doi.org/10.1109/ISDPE.2007.128

The FPGA implementation of 128-bits AES algorithm based on four 32-bits parallel operation. / Huang, Chi-Wu; Chang, Chi Jeng; Lin, Mao Yuan; Tai, Hung Yun.

Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007. 2007. p. 462-464 4402734 (Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Huang, C-W, Chang, CJ, Lin, MY & Tai, HY 2007, The FPGA implementation of 128-bits AES algorithm based on four 32-bits parallel operation. in Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007., 4402734, Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007, pp. 462-464, 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007, Chengdu, China, 07/11/1. https://doi.org/10.1109/ISDPE.2007.128
Huang C-W, Chang CJ, Lin MY, Tai HY. The FPGA implementation of 128-bits AES algorithm based on four 32-bits parallel operation. In Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007. 2007. p. 462-464. 4402734. (Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007). https://doi.org/10.1109/ISDPE.2007.128
Huang, Chi-Wu ; Chang, Chi Jeng ; Lin, Mao Yuan ; Tai, Hung Yun. / The FPGA implementation of 128-bits AES algorithm based on four 32-bits parallel operation. Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007. 2007. pp. 462-464 (Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007).
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