The fabrication of poly-Si MOSFETs using ultra-thin high-K/metal-gate stack for monolithic 3D integrated circuits technology applications

The 3D-ICs have been believed as one of candidates for IC structures to beyond Moore's law as scaling down to reach physic limitation in the future. The sequential process of monolithic 3D-ICs has the advantage of low cost as compare with wafer bonding process. Recently, poly-Ge with high mobility had been reported for monolithic 3D ICs [1], the worse on/off ratio due to high transistor leakage is an issue to development. The high performance upper transistors will be developed to compatible with CMOSFETs of base layer, high-K/metal gate (HK/MG) poly-Si MOSFET could be a solution (Fig. 1). With the experience of flat panel display, the poly-Si TFTs have the property of low temperature process to meet the requirement of monolithic 3D-ICs, which is processing after base transistors. However, hafnium based oxide becomes a mainstream to develop high-K gate-dielectric material in MOSFET due to its high-K value ( 25), widebandgap, acceptable band alignment, and superior thermal stability. The poly-Si TFTs with thick hafnium based oxide ( 20 nm) have been reported the subthreshold swing (SS) as 280 mV/dec [2] and 300 mV/dec [3] for n-channel and p-channel, respectively. In this work, we will integrate ultra-thin HfSiO _x and TiN gate stack with poly-Si for high performance applications, such as monolithic 3D-ICs, and system on glass (SOG).