The fabrication and the reliability of poly-Si MOSFETs using ultra-thin high-K/metal-gate stack

M. H. Lee; K. J. Chen

doi:10.1016/j.sse.2012.07.009

The fabrication and the reliability of poly-Si MOSFETs using ultra-thin high-K/metal-gate stack

M. H. Lee^*, K. J. Chen

^*Corresponding author for this work

Undergraduate Program of Electro-Optical Engineering

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

Poly-Si MOSFETs using a gate stack composed of ultra-thin HfSiO_x and TiN are shown, and they are compatible with a monolithic three-dimensional integrated circuit (3D-ICs) process with the highest thermal budget of 700 °C. The poly-Si MOSFETs were studied for fabrication process temperatures with parasitic resistance, effective gate length, and grain boundary trap density. The short-channel effect with V_T (threshold voltage), subthreshold swing (SS), and drain-induced barrier lowering (DIBL) was also compared at 650 °C and 700 °C. For stress reliability of both hot carrier and PBTI, the short-channel devices showed more stability in V _T than the long-channel devices due to less grain boundary scattering. This study promotes the ultra-thin high-K/metal gate poly-Si MOSFET as a candidate for future monolithic 3D-ICs and silicon-on-glass (SOG) applications.

Original language	English
Pages (from-to)	244-247
Number of pages	4
Journal	Solid-State Electronics
Volume	79
DOIs	https://doi.org/10.1016/j.sse.2012.07.009
Publication status	Published - 2013 Jan

Keywords

3D-ICs
High-K
Poly-Si
Reliability

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

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10.1016/j.sse.2012.07.009

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title = "The fabrication and the reliability of poly-Si MOSFETs using ultra-thin high-K/metal-gate stack",

abstract = "Poly-Si MOSFETs using a gate stack composed of ultra-thin HfSiOx and TiN are shown, and they are compatible with a monolithic three-dimensional integrated circuit (3D-ICs) process with the highest thermal budget of 700 °C. The poly-Si MOSFETs were studied for fabrication process temperatures with parasitic resistance, effective gate length, and grain boundary trap density. The short-channel effect with VT (threshold voltage), subthreshold swing (SS), and drain-induced barrier lowering (DIBL) was also compared at 650 °C and 700 °C. For stress reliability of both hot carrier and PBTI, the short-channel devices showed more stability in V T than the long-channel devices due to less grain boundary scattering. This study promotes the ultra-thin high-K/metal gate poly-Si MOSFET as a candidate for future monolithic 3D-ICs and silicon-on-glass (SOG) applications.",

keywords = "3D-ICs, High-K, Poly-Si, Reliability",

author = "Lee, {M. H.} and Chen, {K. J.}",

note = "Funding Information: The authors are very grateful for funding support by National Science Council, (NSC 101-2221-E-003-019), National Taiwan Normal University (NTNU100-D-01) and experimental support by National Nano Device Laboratories (NDL), Taiwan.",

year = "2013",

month = jan,

doi = "10.1016/j.sse.2012.07.009",

language = "English",

volume = "79",

pages = "244--247",

journal = "Solid-State Electronics",

issn = "0038-1101",

publisher = "Elsevier Limited",

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AU - Lee, M. H.

AU - Chen, K. J.

N1 - Funding Information: The authors are very grateful for funding support by National Science Council, (NSC 101-2221-E-003-019), National Taiwan Normal University (NTNU100-D-01) and experimental support by National Nano Device Laboratories (NDL), Taiwan.

PY - 2013/1

Y1 - 2013/1

N2 - Poly-Si MOSFETs using a gate stack composed of ultra-thin HfSiOx and TiN are shown, and they are compatible with a monolithic three-dimensional integrated circuit (3D-ICs) process with the highest thermal budget of 700 °C. The poly-Si MOSFETs were studied for fabrication process temperatures with parasitic resistance, effective gate length, and grain boundary trap density. The short-channel effect with VT (threshold voltage), subthreshold swing (SS), and drain-induced barrier lowering (DIBL) was also compared at 650 °C and 700 °C. For stress reliability of both hot carrier and PBTI, the short-channel devices showed more stability in V T than the long-channel devices due to less grain boundary scattering. This study promotes the ultra-thin high-K/metal gate poly-Si MOSFET as a candidate for future monolithic 3D-ICs and silicon-on-glass (SOG) applications.

AB - Poly-Si MOSFETs using a gate stack composed of ultra-thin HfSiOx and TiN are shown, and they are compatible with a monolithic three-dimensional integrated circuit (3D-ICs) process with the highest thermal budget of 700 °C. The poly-Si MOSFETs were studied for fabrication process temperatures with parasitic resistance, effective gate length, and grain boundary trap density. The short-channel effect with VT (threshold voltage), subthreshold swing (SS), and drain-induced barrier lowering (DIBL) was also compared at 650 °C and 700 °C. For stress reliability of both hot carrier and PBTI, the short-channel devices showed more stability in V T than the long-channel devices due to less grain boundary scattering. This study promotes the ultra-thin high-K/metal gate poly-Si MOSFET as a candidate for future monolithic 3D-ICs and silicon-on-glass (SOG) applications.

KW - 3D-ICs

KW - High-K

KW - Poly-Si

KW - Reliability

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U2 - 10.1016/j.sse.2012.07.009

DO - 10.1016/j.sse.2012.07.009

M3 - Article

AN - SCOPUS:84869490307

SN - 0038-1101

VL - 79

SP - 244

EP - 247

JO - Solid-State Electronics

JF - Solid-State Electronics

ER -

The fabrication and the reliability of poly-Si MOSFETs using ultra-thin high-K/metal-gate stack

Abstract

Keywords

ASJC Scopus subject areas

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