The fabrication and the reliability of poly-Si MOSFETs using ultra-thin high-K/metal-gate stack

M. H. Lee, K. J. Chen

    Research output: Contribution to journalArticlepeer-review

    1 Citation (Scopus)

    Abstract

    Poly-Si MOSFETs using a gate stack composed of ultra-thin HfSiOx and TiN are shown, and they are compatible with a monolithic three-dimensional integrated circuit (3D-ICs) process with the highest thermal budget of 700 °C. The poly-Si MOSFETs were studied for fabrication process temperatures with parasitic resistance, effective gate length, and grain boundary trap density. The short-channel effect with VT (threshold voltage), subthreshold swing (SS), and drain-induced barrier lowering (DIBL) was also compared at 650 °C and 700 °C. For stress reliability of both hot carrier and PBTI, the short-channel devices showed more stability in V T than the long-channel devices due to less grain boundary scattering. This study promotes the ultra-thin high-K/metal gate poly-Si MOSFET as a candidate for future monolithic 3D-ICs and silicon-on-glass (SOG) applications.

    Original languageEnglish
    Pages (from-to)244-247
    Number of pages4
    JournalSolid-State Electronics
    Volume79
    DOIs
    Publication statusPublished - 2013 Jan 1

    Keywords

    • 3D-ICs
    • High-K
    • Poly-Si
    • Reliability

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Condensed Matter Physics
    • Electrical and Electronic Engineering
    • Materials Chemistry

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