The enhancement of MOSFET electric performance through strain engineering by refilled sige as Source and Drain

Hsin Chia Yang, Chao Wang Li, Wen Shiang Liao, Chong Kuan Du, Mu Chun Wang, Jie Min Yang, Chun Wei Lian, Chuan-Hsi Liu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Mismatched lattice constants between SiGe and silicon can cause the strain making the mobility improved. SiGe are grown underneath the channel apparently to form global strain over the whole devices, while Source/Drain refilled with SiGe would squeeze or pull up the devices uni-axially. The ID-V G characteristics curves and the maximum trans-conductance (g m) using strain engineering are observed to be superior to the baseline. Nevertheless, the breakdown voltages with strain engineering no longer enjoy as robustly as ones without.

Original languageEnglish
Title of host publicationProceedings of the 2013 IEEE 5th International Nanoelectronics Conference, INEC 2013
Pages251-253
Number of pages3
DOIs
Publication statusPublished - 2013 Mar 13
Event2013 IEEE 5th International Nanoelectronics Conference, INEC 2013 - Singapore, Singapore
Duration: 2013 Jan 22013 Jan 4

Publication series

NameProceedings - Winter Simulation Conference
ISSN (Print)0891-7736

Other

Other2013 IEEE 5th International Nanoelectronics Conference, INEC 2013
CountrySingapore
CitySingapore
Period13/1/213/1/4

Fingerprint

SiGe
MOSFET
Enhancement
Engineering
Characteristic Curve
Conductance
Electric breakdown
Lattice constants
Breakdown
Baseline
Silicon
Voltage

Keywords

  • SiGe-Refilled Source/Drain
  • Strained Engineering

ASJC Scopus subject areas

  • Software
  • Modelling and Simulation
  • Computer Science Applications

Cite this

Yang, H. C., Li, C. W., Liao, W. S., Du, C. K., Wang, M. C., Yang, J. M., ... Liu, C-H. (2013). The enhancement of MOSFET electric performance through strain engineering by refilled sige as Source and Drain. In Proceedings of the 2013 IEEE 5th International Nanoelectronics Conference, INEC 2013 (pp. 251-253). [6466014] (Proceedings - Winter Simulation Conference). https://doi.org/10.1109/INEC.2013.6466014

The enhancement of MOSFET electric performance through strain engineering by refilled sige as Source and Drain. / Yang, Hsin Chia; Li, Chao Wang; Liao, Wen Shiang; Du, Chong Kuan; Wang, Mu Chun; Yang, Jie Min; Lian, Chun Wei; Liu, Chuan-Hsi.

Proceedings of the 2013 IEEE 5th International Nanoelectronics Conference, INEC 2013. 2013. p. 251-253 6466014 (Proceedings - Winter Simulation Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yang, HC, Li, CW, Liao, WS, Du, CK, Wang, MC, Yang, JM, Lian, CW & Liu, C-H 2013, The enhancement of MOSFET electric performance through strain engineering by refilled sige as Source and Drain. in Proceedings of the 2013 IEEE 5th International Nanoelectronics Conference, INEC 2013., 6466014, Proceedings - Winter Simulation Conference, pp. 251-253, 2013 IEEE 5th International Nanoelectronics Conference, INEC 2013, Singapore, Singapore, 13/1/2. https://doi.org/10.1109/INEC.2013.6466014
Yang HC, Li CW, Liao WS, Du CK, Wang MC, Yang JM et al. The enhancement of MOSFET electric performance through strain engineering by refilled sige as Source and Drain. In Proceedings of the 2013 IEEE 5th International Nanoelectronics Conference, INEC 2013. 2013. p. 251-253. 6466014. (Proceedings - Winter Simulation Conference). https://doi.org/10.1109/INEC.2013.6466014
Yang, Hsin Chia ; Li, Chao Wang ; Liao, Wen Shiang ; Du, Chong Kuan ; Wang, Mu Chun ; Yang, Jie Min ; Lian, Chun Wei ; Liu, Chuan-Hsi. / The enhancement of MOSFET electric performance through strain engineering by refilled sige as Source and Drain. Proceedings of the 2013 IEEE 5th International Nanoelectronics Conference, INEC 2013. 2013. pp. 251-253 (Proceedings - Winter Simulation Conference).
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