The analysis of the process-induced channel stress in N-MOSFET

Ming-Jenq Twu, R. H. Deng, Z. H. Chen, M. C. Tsai, K. C. Lin, Chuan-Hsi Liu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This research analyzes internal stress in the N-MOSFET. The research has two parts. First, we explore the effect of N-MOSFET channel stress when CESL layer is not utilized. The dimensional effect of spacer upon channel stress in N-MOSFET with variant width of ONO (oxide, nitride, oxide) is compared. Second, with stress applied to CESL and the spacer stressor, long/short channel effects are analyzed. It is demonstrated that when the thickness of CESL and the height of gate increase, the channel stress under the gate dielectric layer becomes tensile, and the performance is improved in the short channel, resulting in the improved performance in the whole N-MOSFET. Therefore, better device characteristics can be expected through the approach disclosed in this paper.

Original languageEnglish
Title of host publicationMaterials Science and Chemical Engineering
Pages440-444
Number of pages5
DOIs
Publication statusPublished - 2013 Jul 8
Event2013 International Conference on Materials Science and Chemical Engineering, MSCE 2013 - , Singapore
Duration: 2013 Feb 202013 Feb 21

Publication series

NameAdvanced Materials Research
Volume699
ISSN (Print)1022-6680

Other

Other2013 International Conference on Materials Science and Chemical Engineering, MSCE 2013
CountrySingapore
Period13/2/2013/2/21

Keywords

  • CESL (contact etch stop layer)
  • Channel stress
  • N-MOSFET
  • Spacer stressor

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Twu, M-J., Deng, R. H., Chen, Z. H., Tsai, M. C., Lin, K. C., & Liu, C-H. (2013). The analysis of the process-induced channel stress in N-MOSFET. In Materials Science and Chemical Engineering (pp. 440-444). (Advanced Materials Research; Vol. 699). https://doi.org/10.4028/www.scientific.net/AMR.699.440