The Moore's law has successfully predicted the trend of semiconductor-device shrinkage in the past five decades. As the fabrication techniques' advances, the shrinkage limitations maybe hit in the following decade(s). The Gate-All-Around Field-Effect Transistor (GAA-FET) is an important device which can extend the Moore's law by overcoming technical deficiencies of the fabrication techniques as well as improve the device performance. From the aspect of patent landscaping, acquiring techniques of GAA-FET is very important for the development and provision of the next generation of technology for logic products. Albeit important, very few works discussed the patent analysis, landscaping, and roadmapping of techniques for GAA-FET. To cross the research gap, this work will propose a novel technology roadmapping framework based on the patent mining techniques as well as algorithms for solving the fuzzy knapsack and the fuzzy competence set expansion problems. At first, related U.S. patents will be retrieved. Then, an algorithm to resolve the Fuzzy Knapsack Problem (FKP) is used to select the most appropriate GAA-FET techniques to design around. After that, an algorithm for the fuzzy competence set expansion is adopted to design a minimum spanning tree (MST). The MST can serve as the basis for developing a technology roadmap for developing GAA-FET techniques for late coming semiconductor foundries. The empirical study derived a patent portfolio consisting of 12 techniques related to the GAA-FET. The derived patent portfolio as well as the MST can serve as the basis for defining design-around strategies and technology roadmaps by fast catching-up semiconductor foundries.