Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology

Chun Yu Lin; Ming Dou Ker; Pin Hsin Chang; Wen Tai Wang

doi:10.1109/NMDC.2015.7439250

Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology

Chun Yu Lin, Ming Dou Ker, Pin Hsin Chang, Wen Tai Wang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Citations (Scopus)

Abstract

To protect the IC chips against the electrostatic discharge (ESD) damages in 28nm high-k metal-gate (HKMG) CMOS technology, the ESD protection consideration was studied in this work. The ESD design window was found to be within 1V and 5.1V in 28nm HKMG CMOS technology. An ESD protection device of PMOS with embedded silicon-controlled rectifier (SCR) was investigated to be suitable for ESD protection in such narrow ESD design window.

Original language	English
Title of host publication	2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781467393621
DOIs	https://doi.org/10.1109/NMDC.2015.7439250
Publication status	Published - 2016 Mar 22
Event	10th IEEE Nanotechnology Materials and Devices Conference, NMDC 2015 - Anchorage, United States Duration: 2015 Sept 12 → 2015 Sept 16

Publication series

Name	2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015

Other

Other	10th IEEE Nanotechnology Materials and Devices Conference, NMDC 2015
Country/Territory	United States
City	Anchorage
Period	2015/09/12 → 2015/09/16

Keywords

CMOS
electrostatic discharge (ESD)
high-k metal-gate (HKMG)
silicon-controlled rectifier (SCR)

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/NMDC.2015.7439250

Cite this

Lin, C. Y., Ker, M. D., Chang, P. H., & Wang, W. T. (2016). Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology. In 2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015 Article 7439250 (2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/NMDC.2015.7439250

Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology. / Lin, Chun Yu; Ker, Ming Dou; Chang, Pin Hsin et al.
2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015. Institute of Electrical and Electronics Engineers Inc., 2016. 7439250 (2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Lin, CY, Ker, MD, Chang, PH & Wang, WT 2016, Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology. in 2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015., 7439250, 2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015, Institute of Electrical and Electronics Engineers Inc., 10th IEEE Nanotechnology Materials and Devices Conference, NMDC 2015, Anchorage, United States, 2015/09/12. https://doi.org/10.1109/NMDC.2015.7439250

Lin CY, Ker MD, Chang PH, Wang WT. Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology. In 2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015. Institute of Electrical and Electronics Engineers Inc. 2016. 7439250. (2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015). doi: 10.1109/NMDC.2015.7439250

Lin, Chun Yu ; Ker, Ming Dou ; Chang, Pin Hsin et al. / Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology. 2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015. Institute of Electrical and Electronics Engineers Inc., 2016. (2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015).

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title = "Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology",

abstract = "To protect the IC chips against the electrostatic discharge (ESD) damages in 28nm high-k metal-gate (HKMG) CMOS technology, the ESD protection consideration was studied in this work. The ESD design window was found to be within 1V and 5.1V in 28nm HKMG CMOS technology. An ESD protection device of PMOS with embedded silicon-controlled rectifier (SCR) was investigated to be suitable for ESD protection in such narrow ESD design window.",

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AB - To protect the IC chips against the electrostatic discharge (ESD) damages in 28nm high-k metal-gate (HKMG) CMOS technology, the ESD protection consideration was studied in this work. The ESD design window was found to be within 1V and 5.1V in 28nm HKMG CMOS technology. An ESD protection device of PMOS with embedded silicon-controlled rectifier (SCR) was investigated to be suitable for ESD protection in such narrow ESD design window.

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KW - silicon-controlled rectifier (SCR)

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Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology

Abstract

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