Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology

Chun Yu Lin, Ming Dou Ker, Pin Hsin Chang, Wen Tai Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

To protect the IC chips against the electrostatic discharge (ESD) damages in 28nm high-k metal-gate (HKMG) CMOS technology, the ESD protection consideration was studied in this work. The ESD design window was found to be within 1V and 5.1V in 28nm HKMG CMOS technology. An ESD protection device of PMOS with embedded silicon-controlled rectifier (SCR) was investigated to be suitable for ESD protection in such narrow ESD design window.

Original languageEnglish
Title of host publication2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467393621
DOIs
Publication statusPublished - 2016 Mar 22
Event10th IEEE Nanotechnology Materials and Devices Conference, NMDC 2015 - Anchorage, United States
Duration: 2015 Sep 122015 Sep 16

Publication series

Name2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015

Other

Other10th IEEE Nanotechnology Materials and Devices Conference, NMDC 2015
CountryUnited States
CityAnchorage
Period15/9/1215/9/16

Fingerprint

Electrostatic discharge
Oxides
Metals
Thyristors

Keywords

  • CMOS
  • electrostatic discharge (ESD)
  • high-k metal-gate (HKMG)
  • silicon-controlled rectifier (SCR)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Lin, C. Y., Ker, M. D., Chang, P. H., & Wang, W. T. (2016). Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology. In 2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015 [7439250] (2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/NMDC.2015.7439250

Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology. / Lin, Chun Yu; Ker, Ming Dou; Chang, Pin Hsin; Wang, Wen Tai.

2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015. Institute of Electrical and Electronics Engineers Inc., 2016. 7439250 (2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lin, CY, Ker, MD, Chang, PH & Wang, WT 2016, Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology. in 2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015., 7439250, 2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015, Institute of Electrical and Electronics Engineers Inc., 10th IEEE Nanotechnology Materials and Devices Conference, NMDC 2015, Anchorage, United States, 15/9/12. https://doi.org/10.1109/NMDC.2015.7439250
Lin CY, Ker MD, Chang PH, Wang WT. Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology. In 2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015. Institute of Electrical and Electronics Engineers Inc. 2016. 7439250. (2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015). https://doi.org/10.1109/NMDC.2015.7439250
Lin, Chun Yu ; Ker, Ming Dou ; Chang, Pin Hsin ; Wang, Wen Tai. / Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology. 2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015. Institute of Electrical and Electronics Engineers Inc., 2016. (2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015).
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abstract = "To protect the IC chips against the electrostatic discharge (ESD) damages in 28nm high-k metal-gate (HKMG) CMOS technology, the ESD protection consideration was studied in this work. The ESD design window was found to be within 1V and 5.1V in 28nm HKMG CMOS technology. An ESD protection device of PMOS with embedded silicon-controlled rectifier (SCR) was investigated to be suitable for ESD protection in such narrow ESD design window.",
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