Strained CMOS technology with Ge

P. S. Chen, Min-Hung Lee, S. W. Lee, C. W. Liu, M. J. Tsai

    Research output: Contribution to conferencePaperpeer-review


    The strained CMOSFETs with the addition of Ge have been achieved by introducing Si/SiGe quantum well, Si:C/SiGe quantum well and multiple Ge/Si bilayers as bottom Stressor. It is found that the Si/SiGe nanostructure changes the relaxation mechanism during the growth so that the shrinkage of relaxed SiGe thickness can be done. Such relaxed SiGe buffers on these novel Si/SiGe have a reading dislocation density of 105∼106 cm -2. The Si/SiGe nanostructures act as an effective nucleation site for misfit dislocation to release the mismatch strain. Effective electron mobility for the strained-Si device with Si/SiGe quantum well (SI), Si 0.996C0.014/SiGe quantum well (SIC), and the multiple Ge quantum dot (MQD) buffer layer are found to be 80, 95, 82% higher than that of Si control device, respectively. The scheme to form the relaxed SiGe film serving as a virtual substrate shall be applicable to high-speed strained-Si devices. For the application of transport enhanced devices, high quality of thin strained Ge on Si (100) (GOS) has also been successfully demonstrated by similar strain engineering between Si and Ge epilayers in this study. The effective hole mobility for strained Ge pMOSFET with Pt Schottky barrier (SB) source and drain contact is found to be 3.3 X higher than that of Si control device.

    Original languageEnglish
    Number of pages10
    Publication statusPublished - 2005 Dec 1
    Event207th ECS Meeting - Quebec, Canada
    Duration: 2005 May 162005 May 20


    Other207th ECS Meeting

    ASJC Scopus subject areas

    • Engineering(all)

    Fingerprint Dive into the research topics of 'Strained CMOS technology with Ge'. Together they form a unique fingerprint.

    Cite this