Strained CMOS technology with Ge

P. S. Chen, Min-Hung Lee, S. W. Lee, C. W. Liu, M. J. Tsai

Research output: Contribution to conferencePaper

Abstract

The strained CMOSFETs with the addition of Ge have been achieved by introducing Si/SiGe quantum well, Si:C/SiGe quantum well and multiple Ge/Si bilayers as bottom Stressor. It is found that the Si/SiGe nanostructure changes the relaxation mechanism during the growth so that the shrinkage of relaxed SiGe thickness can be done. Such relaxed SiGe buffers on these novel Si/SiGe have a reading dislocation density of 105∼106 cm -2. The Si/SiGe nanostructures act as an effective nucleation site for misfit dislocation to release the mismatch strain. Effective electron mobility for the strained-Si device with Si/SiGe quantum well (SI), Si 0.996C0.014/SiGe quantum well (SIC), and the multiple Ge quantum dot (MQD) buffer layer are found to be 80, 95, 82% higher than that of Si control device, respectively. The scheme to form the relaxed SiGe film serving as a virtual substrate shall be applicable to high-speed strained-Si devices. For the application of transport enhanced devices, high quality of thin strained Ge on Si (100) (GOS) has also been successfully demonstrated by similar strain engineering between Si and Ge epilayers in this study. The effective hole mobility for strained Ge pMOSFET with Pt Schottky barrier (SB) source and drain contact is found to be 3.3 X higher than that of Si control device.

Original languageEnglish
Pages487-496
Number of pages10
Publication statusPublished - 2005 Dec 1
Event207th ECS Meeting - Quebec, Canada
Duration: 2005 May 162005 May 20

Other

Other207th ECS Meeting
CountryCanada
CityQuebec
Period05/5/1605/5/20

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Semiconductor quantum wells
Nanostructures
Hole mobility
Epilayers
Electron mobility
Buffer layers
Dislocations (crystals)
Semiconductor quantum dots
Nucleation
Substrates

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Chen, P. S., Lee, M-H., Lee, S. W., Liu, C. W., & Tsai, M. J. (2005). Strained CMOS technology with Ge. 487-496. Paper presented at 207th ECS Meeting, Quebec, Canada.

Strained CMOS technology with Ge. / Chen, P. S.; Lee, Min-Hung; Lee, S. W.; Liu, C. W.; Tsai, M. J.

2005. 487-496 Paper presented at 207th ECS Meeting, Quebec, Canada.

Research output: Contribution to conferencePaper

Chen, PS, Lee, M-H, Lee, SW, Liu, CW & Tsai, MJ 2005, 'Strained CMOS technology with Ge', Paper presented at 207th ECS Meeting, Quebec, Canada, 05/5/16 - 05/5/20 pp. 487-496.
Chen PS, Lee M-H, Lee SW, Liu CW, Tsai MJ. Strained CMOS technology with Ge. 2005. Paper presented at 207th ECS Meeting, Quebec, Canada.
Chen, P. S. ; Lee, Min-Hung ; Lee, S. W. ; Liu, C. W. ; Tsai, M. J. / Strained CMOS technology with Ge. Paper presented at 207th ECS Meeting, Quebec, Canada.10 p.
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AB - The strained CMOSFETs with the addition of Ge have been achieved by introducing Si/SiGe quantum well, Si:C/SiGe quantum well and multiple Ge/Si bilayers as bottom Stressor. It is found that the Si/SiGe nanostructure changes the relaxation mechanism during the growth so that the shrinkage of relaxed SiGe thickness can be done. Such relaxed SiGe buffers on these novel Si/SiGe have a reading dislocation density of 105∼106 cm -2. The Si/SiGe nanostructures act as an effective nucleation site for misfit dislocation to release the mismatch strain. Effective electron mobility for the strained-Si device with Si/SiGe quantum well (SI), Si 0.996C0.014/SiGe quantum well (SIC), and the multiple Ge quantum dot (MQD) buffer layer are found to be 80, 95, 82% higher than that of Si control device, respectively. The scheme to form the relaxed SiGe film serving as a virtual substrate shall be applicable to high-speed strained-Si devices. For the application of transport enhanced devices, high quality of thin strained Ge on Si (100) (GOS) has also been successfully demonstrated by similar strain engineering between Si and Ge epilayers in this study. The effective hole mobility for strained Ge pMOSFET with Pt Schottky barrier (SB) source and drain contact is found to be 3.3 X higher than that of Si control device.

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