Single-electron transistor using self-aligned sidewall spacer gates on silicon-on-insulator nanowire

S. F. Hu*, Y. C. Wu, C. L. Sung, C. Y. Chang, T. Y. Huang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

A dual-gate-controlled single-electron transistor was fabricated by using self-aligned polysilicon sidewall spacer gates on a silicon-on-insulator nanowire. The quantum dot formed by the electric field effect of the dual-gate structure was miniaturized to smaller than the state-of-the-art feature size, through a combination of electron beam lithography, oxidation and polysilicon sidewall spacer gate formation processes. The device shows typical MOSFET I-V characteristics at room temperature. However, the Coulomb gap and Coulomb oscillations are clearly observed at 4 K.

Original languageEnglish
Title of host publication2003 3rd IEEE Conference on Nanotechnology, IEEE-NANO 2003 - Proceedings
PublisherIEEE Computer Society
Pages573-576
Number of pages4
ISBN (Electronic)0780379764
DOIs
Publication statusPublished - 2003
Externally publishedYes
Event2003 3rd IEEE Conference on Nanotechnology, IEEE-NANO 2003 - San Francisco, United States
Duration: 2003 Aug 122003 Aug 14

Publication series

NameProceedings of the IEEE Conference on Nanotechnology
Volume2
ISSN (Print)1944-9399
ISSN (Electronic)1944-9380

Other

Other2003 3rd IEEE Conference on Nanotechnology, IEEE-NANO 2003
Country/TerritoryUnited States
CitySan Francisco
Period2003/08/122003/08/14

Keywords

  • Electron beams
  • Lithography
  • Nanoscale devices
  • Oxidation
  • Quantum dots
  • Silicon on insulator technology
  • Single electron transistors
  • Size control
  • Temperature
  • Wires

ASJC Scopus subject areas

  • Bioengineering
  • Electrical and Electronic Engineering
  • Materials Chemistry
  • Condensed Matter Physics

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