Simulation-based study of negative-capacitance double-gate tunnel field-effect transistor with ferroelectric gate stack

Chien Liu, Ping Guang Chen, Meng Jie Xie, Shao Nong Liu, Jun Wei Lee, Shao Jia Huang, Sally Liu, Yu Sheng Chen, Heng Yuan Lee, Ming Han Liao, Pang Shiu Chen, Min Hung Lee

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Abstract

The concept of ferroelectric (FE) negative capacitance (NC) may be a turning point in overcoming the physical limitations imposed by the Boltzmann tyranny to realize next-generation state-of-the-art devices. Both the body factor (m-factor) and the transport mechanism (n-factor) are simultaneously improved by integrating an NC with a tunnel FET (TFET). The modeling approach is discussed in this study as well as the NC physics. By optimizing the thicknesses of FE, semiconductor, and interfacial layers, the capacitance of the FE layers is modulated to match that of a MOS resulting in the smallest subthreshold swing that is also hysteresis-free. An ultrathin-body double gate tunnel FET (UTB-DG-TFET) exhibits a steep slope (a subthreshold swing below 10mV/dec over more than 4 orders of magnitude) for low-power applications (<0.2V switching voltage) to realize next-generation state-of-the-art devices.

Original languageEnglish
Article number04EB08
JournalJapanese Journal of Applied Physics
Volume55
Issue number4
DOIs
Publication statusPublished - 2016 Apr

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ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy(all)

Cite this

Liu, C., Chen, P. G., Xie, M. J., Liu, S. N., Lee, J. W., Huang, S. J., Liu, S., Chen, Y. S., Lee, H. Y., Liao, M. H., Chen, P. S., & Lee, M. H. (2016). Simulation-based study of negative-capacitance double-gate tunnel field-effect transistor with ferroelectric gate stack. Japanese Journal of Applied Physics, 55(4), [04EB08]. https://doi.org/10.7567/JJAP.55.04EB08