Si-capping thicknesses impacting compressive strained MOSFETs with temperature effect

Mu Chun Wang; Ssu Hao Peng; Shea Jue Wang; Hsin Chia Yang; Wen Shiang Liao; Chao Wang Li; Chuan Hsi Liu

doi:10.1109/ISNE.2013.6512367

Si-capping thicknesses impacting compressive strained MOSFETs with temperature effect

Mu Chun Wang, Ssu Hao Peng, Shea Jue Wang^*, Hsin Chia Yang, Wen Shiang Liao, Chao Wang Li, Chuan Hsi Liu

^*Corresponding author for this work

Department of Mechatronic Engineering

Research output: Contribution to conference › Paper › peer-review

Abstract

Increasing the electrical performance of the MOSFETs with contact etch stop layer (CESL) and SiGe channel technologies in strain engineering is indeed approached. Using silicon capping layer performs the benefits on the smoothness of channel surface and the prevention of germanium penetration from SiGe layer. In this study, the deposited capping layer thicknesses with SiGe channel of (110) substrate wafer were 1.5 and 3.0 nm on the poly gate. The interesting device parameters including drive current, transconductance, threshold voltage (V_T) and subthreshold swing (S.S.) with temperature effect are systematically analyzed.

Original language	English
Pages	361-364
Number of pages	4
DOIs	https://doi.org/10.1109/ISNE.2013.6512367
Publication status	Published - 2013
Event	2013 IEEE International Symposium on Next-Generation Electronics, ISNE 2013 - Kaohsiung, Taiwan Duration: 2013 Feb 25 → 2013 Feb 26

Other

Other	2013 IEEE International Symposium on Next-Generation Electronics, ISNE 2013
Country/Territory	Taiwan
City	Kaohsiung
Period	2013/02/25 → 2013/02/26

Keywords

contact etching stop layer (CESL)
mobility
silicon capping layer
strained silicon

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/ISNE.2013.6512367

Cite this

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title = "Si-capping thicknesses impacting compressive strained MOSFETs with temperature effect",

abstract = "Increasing the electrical performance of the MOSFETs with contact etch stop layer (CESL) and SiGe channel technologies in strain engineering is indeed approached. Using silicon capping layer performs the benefits on the smoothness of channel surface and the prevention of germanium penetration from SiGe layer. In this study, the deposited capping layer thicknesses with SiGe channel of (110) substrate wafer were 1.5 and 3.0 nm on the poly gate. The interesting device parameters including drive current, transconductance, threshold voltage (VT) and subthreshold swing (S.S.) with temperature effect are systematically analyzed.",

keywords = "contact etching stop layer (CESL), mobility, silicon capping layer, strained silicon",

author = "Wang, {Mu Chun} and Peng, {Ssu Hao} and Wang, {Shea Jue} and Yang, {Hsin Chia} and Liao, {Wen Shiang} and Li, {Chao Wang} and Liu, {Chuan Hsi}",

year = "2013",

doi = "10.1109/ISNE.2013.6512367",

language = "English",

pages = "361--364",

note = "2013 IEEE International Symposium on Next-Generation Electronics, ISNE 2013 ; Conference date: 25-02-2013 Through 26-02-2013",

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TY - CONF

T1 - Si-capping thicknesses impacting compressive strained MOSFETs with temperature effect

AU - Wang, Mu Chun

AU - Peng, Ssu Hao

AU - Wang, Shea Jue

AU - Yang, Hsin Chia

AU - Liao, Wen Shiang

AU - Li, Chao Wang

AU - Liu, Chuan Hsi

PY - 2013

Y1 - 2013

N2 - Increasing the electrical performance of the MOSFETs with contact etch stop layer (CESL) and SiGe channel technologies in strain engineering is indeed approached. Using silicon capping layer performs the benefits on the smoothness of channel surface and the prevention of germanium penetration from SiGe layer. In this study, the deposited capping layer thicknesses with SiGe channel of (110) substrate wafer were 1.5 and 3.0 nm on the poly gate. The interesting device parameters including drive current, transconductance, threshold voltage (VT) and subthreshold swing (S.S.) with temperature effect are systematically analyzed.

AB - Increasing the electrical performance of the MOSFETs with contact etch stop layer (CESL) and SiGe channel technologies in strain engineering is indeed approached. Using silicon capping layer performs the benefits on the smoothness of channel surface and the prevention of germanium penetration from SiGe layer. In this study, the deposited capping layer thicknesses with SiGe channel of (110) substrate wafer were 1.5 and 3.0 nm on the poly gate. The interesting device parameters including drive current, transconductance, threshold voltage (VT) and subthreshold swing (S.S.) with temperature effect are systematically analyzed.

KW - contact etching stop layer (CESL)

KW - mobility

KW - silicon capping layer

KW - strained silicon

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U2 - 10.1109/ISNE.2013.6512367

DO - 10.1109/ISNE.2013.6512367

M3 - Paper

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SP - 361

EP - 364

T2 - 2013 IEEE International Symposium on Next-Generation Electronics, ISNE 2013

Y2 - 25 February 2013 through 26 February 2013

ER -

Si-capping thicknesses impacting compressive strained MOSFETs with temperature effect

Abstract

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Keywords

ASJC Scopus subject areas

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