Si-capping thicknesses impacting compressive strained MOSFETs with temperature effect

Mu Chun Wang, Ssu Hao Peng, Shea Jue Wang, Hsin Chia Yang, Wen Shiang Liao, Chao Wang Li, Chuan Hsi Liu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Increasing the electrical performance of the MOSFETs with contact etch stop layer (CESL) and SiGe channel technologies in strain engineering is indeed approached. Using silicon capping layer performs the benefits on the smoothness of channel surface and the prevention of germanium penetration from SiGe layer. In this study, the deposited capping layer thicknesses with SiGe channel of (110) substrate wafer were 1.5 and 3.0 nm on the poly gate. The interesting device parameters including drive current, transconductance, threshold voltage (VT) and subthreshold swing (S.S.) with temperature effect are systematically analyzed.

Original languageEnglish
Title of host publicationISNE 2013 - IEEE International Symposium on Next-Generation Electronics 2013
Pages361-364
Number of pages4
DOIs
Publication statusPublished - 2013 May 27
Event2013 IEEE International Symposium on Next-Generation Electronics, ISNE 2013 - Kaohsiung, Taiwan
Duration: 2013 Feb 252013 Feb 26

Other

Other2013 IEEE International Symposium on Next-Generation Electronics, ISNE 2013
CountryTaiwan
CityKaohsiung
Period13/2/2513/2/26

Keywords

  • contact etching stop layer (CESL)
  • mobility
  • silicon capping layer
  • strained silicon

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Wang, M. C., Peng, S. H., Wang, S. J., Yang, H. C., Liao, W. S., Li, C. W., & Liu, C. H. (2013). Si-capping thicknesses impacting compressive strained MOSFETs with temperature effect. In ISNE 2013 - IEEE International Symposium on Next-Generation Electronics 2013 (pp. 361-364). [6512367] https://doi.org/10.1109/ISNE.2013.6512367