TY - GEN
T1 - Shift-or circuit for efficient network intrusion detection pattern matching
AU - Roan, Huang Chun
AU - Hwang, Wen Jyi
AU - Lo, Chia Tien Dan
PY - 2006
Y1 - 2006
N2 - This paper introduces a novel FPGA-based signature match co-processor architecture serving as the core of a hardwarebased network intrusion detection system (NIDS). The signature match co-processor architecture is based on the shift-or algorithm. The architecture is comprised of simple shift registers, or-gates, and ROMs where patterns are stored. As compared with related work, experimental results show that the proposed work achieves higher throughput and less hardware resource in the FPGA implementations of NIDS systems.
AB - This paper introduces a novel FPGA-based signature match co-processor architecture serving as the core of a hardwarebased network intrusion detection system (NIDS). The signature match co-processor architecture is based on the shift-or algorithm. The architecture is comprised of simple shift registers, or-gates, and ROMs where patterns are stored. As compared with related work, experimental results show that the proposed work achieves higher throughput and less hardware resource in the FPGA implementations of NIDS systems.
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U2 - 10.1109/FPL.2006.311314
DO - 10.1109/FPL.2006.311314
M3 - Conference contribution
AN - SCOPUS:46249124852
SN - 142440312X
SN - 9781424403127
T3 - Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL
SP - 785
EP - 790
BT - Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL
T2 - 2006 International Conference on Field Programmable Logic and Applications, FPL
Y2 - 28 August 2006 through 30 August 2006
ER -