Shift-or circuit for efficient network intrusion detection pattern matching

Huang Chun Roan, Wen-Jyi Hwang, Chia Tien Dan Lo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

This paper introduces a novel FPGA-based signature match co-processor architecture serving as the core of a hardwarebased network intrusion detection system (NIDS). The signature match co-processor architecture is based on the shift-or algorithm. The architecture is comprised of simple shift registers, or-gates, and ROMs where patterns are stored. As compared with related work, experimental results show that the proposed work achieves higher throughput and less hardware resource in the FPGA implementations of NIDS systems.

Original languageEnglish
Title of host publicationProceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL
Pages785-790
Number of pages6
DOIs
Publication statusPublished - 2006 Dec 1
Event2006 International Conference on Field Programmable Logic and Applications, FPL - Madrid, Spain
Duration: 2006 Aug 282006 Aug 30

Publication series

NameProceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL

Other

Other2006 International Conference on Field Programmable Logic and Applications, FPL
CountrySpain
CityMadrid
Period06/8/2806/8/30

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ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Electrical and Electronic Engineering

Cite this

Roan, H. C., Hwang, W-J., & Lo, C. T. D. (2006). Shift-or circuit for efficient network intrusion detection pattern matching. In Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL (pp. 785-790). [4101076] (Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL). https://doi.org/10.1109/FPL.2006.311314