Rule-based scheduling in wafer fabrication with due date-based objectives

Tsung Che Chiang, Li Chen Fu

Research output: Contribution to journalArticle

13 Citations (Scopus)

Abstract

Wafer fabrication is a capital-intensive and highly complex manufacturing process. In the wafer fabrication facility (fab), wafers are grouped as a lot to go through repeated sequences of operations to build circuitry. Lot scheduling is an important task for manufacturers to improve production efficiency and meet customers' requirements of on-time delivery. In this research we propose a dispatching rule for lot scheduling in wafer fabs, focusing on three due date-based objectives: on-time delivery rate, mean tardiness, and maximum tardiness. Although many dispatching rules have been proposed in the literature, they usually perform well in some objectives and bad in others. Our rule implements good principles in existing rules by means of (1) an urgency function for a single lot, (2) a priority index function considering total urgency of multiple waiting lots, (3) a due date extension procedure for dealing with tardy lots, and (4) a lot filtering procedure for selecting urgent lots. Simulation experiments are conducted using nine data sets of fabs. Six scenarios formed by two levels of load and three levels of due date tightness are tested for each fab. Performance verification of the proposed rule is achieved by comparing with nine benchmark rules. The experimental results show that the proposed rule outperforms the benchmark rules in terms of all concerned objective functions.

Original languageEnglish
Pages (from-to)2820-2835
Number of pages16
JournalComputers and Operations Research
Volume39
Issue number11
DOIs
Publication statusPublished - 2012 Nov 1

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Keywords

  • Dispatching rules
  • On-time delivery
  • Scheduling
  • Semiconductor manufacturing
  • Tardiness
  • Wafer fabrication

ASJC Scopus subject areas

  • Computer Science(all)
  • Modelling and Simulation
  • Management Science and Operations Research

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