Robust ESD protection design for 40-GB/s transceiver in 65-Nm CMOS process

Chun-Yu Lin, Li Wei Chu, Ming Dou Ker

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

To protect a 40-Gb/s transceiver from electrostatic discharge (ESD) damages, a robust ESD protection design has been proposed and realized in a 65-nm CMOS process. In this paper, diodes are used for ESD protection and inductors are used for high-speed performance fine tuning. Experimental results of the test circuits have been successfully verified, including high-speed performances and ESD robustness. The proposed design has been further applied to a 40-Gb/s current-mode logic (CML) buffer. Verified in silicon chip, the 40-Gb/s CML buffer with the proposed design can achieve good high-speed performance and high ESD robustness.

Original languageEnglish
Article number6588898
Pages (from-to)3625-3631
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume60
Issue number11
DOIs
Publication statusPublished - 2013 Sep 9

Fingerprint

Electrostatic discharge
Transceivers
Buffers
Silicon
Diodes
Tuning
Networks (circuits)

Keywords

  • 40 Gb/s
  • CMOS
  • electrostatic discharge (ESD)
  • high speed

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Robust ESD protection design for 40-GB/s transceiver in 65-Nm CMOS process. / Lin, Chun-Yu; Chu, Li Wei; Ker, Ming Dou.

In: IEEE Transactions on Electron Devices, Vol. 60, No. 11, 6588898, 09.09.2013, p. 3625-3631.

Research output: Contribution to journalArticle

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