Quantum well nanopillar transistors

We have fabricated vertical quantum well nanopillar transistors that consist of a vertical stack of coupled asymmetric quantum wells in a poly-silicon/ silicon nitride multilayer nano-pillars configuration with each well having a unique size. The devices consist of resonant tunneling in the poly-silicon/ silicon nitride stacked pillar material system surrounded by a Schottky gate. The gate electrode surrounds half side of a silicon pillar island, and the channel region exists at all the pillar silicon island. Current-voltage measurements at room temperature show prominent quantum effects due to electron resonance tunneling with side-gate. Accordingly, the vertical transistor offers high-shrinkage feature. By using the occupied area of the ULSI can be shrunk to 10% of that using conventional planar transistor. The small-occupied area leads to the small capacitance and the small load resistance, resulting in high speed and low power operation.