Quantum well nanopillar transistors

Shu Fen Hu*, Chin Lung Sung

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution


We have fabricated vertical quantum well nanopillar transistors that consist of a vertical stack of coupled asymmetric quantum wells in a poly-silicon/ silicon nitride multilayer nano-pillars configuration with each well having a unique size. The devices consist of resonant tunneling in the poly-silicon/ silicon nitride stacked pillar material system surrounded by a Schottky gate. The gate electrode surrounds half side of a silicon pillar island, and the channel region exists at all the pillar silicon island. Current-voltage measurements at room temperature show prominent quantum effects due to electron resonance tunneling with side-gate. Accordingly, the vertical transistor offers high-shrinkage feature. By using the occupied area of the ULSI can be shrunk to 10% of that using conventional planar transistor. The small-occupied area leads to the small capacitance and the small load resistance, resulting in high speed and low power operation.

Original languageEnglish
Title of host publicationTransistor Scaling-Methods, Materials and Modeling
PublisherMaterials Research Society
Number of pages8
ISBN (Print)1558998691, 9781558998698
Publication statusPublished - 2006
Externally publishedYes
Event2006 MRS Spring Meeting - San Francisco, CA, United States
Duration: 2006 Apr 182006 Apr 19

Publication series

NameMaterials Research Society Symposium Proceedings
ISSN (Print)0272-9172


Other2006 MRS Spring Meeting
Country/TerritoryUnited States
CitySan Francisco, CA

ASJC Scopus subject areas

  • Materials Science(all)
  • Condensed Matter Physics
  • Mechanics of Materials
  • Mechanical Engineering


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