Abstract
We have fabricated vertical quantum well nanopillar transistors that consist of a vertical stack of coupled asymmetric quantum wells in a poly-silicon/ silicon nitride multilayer nano-pillars configuration with each well having a unique size. The devices consist of resonant tunneling in the poly-silicon/ silicon nitride stacked pillar material system surrounded by a Schottky gate. The gate electrode surrounds half side of a silicon pillar island, and the channel region exists at all the pillar silicon island. Current-voltage measurements at room temperature show prominent quantum effects due to electron resonance tunneling with side-gate. Accordingly, the vertical transistor offers high-shrinkage feature. By using the occupied area of the ULSI can be shrunk to 10% of that using conventional planar transistor. The small-occupied area leads to the small capacitance and the small load resistance, resulting in high speed and low power operation.
| Original language | English |
|---|---|
| Title of host publication | Transistor Scaling-Methods, Materials and Modeling |
| Pages | 85-92 |
| Number of pages | 8 |
| Publication status | Published - 2006 Dec 1 |
| Event | 2006 MRS Spring Meeting - San Francisco, CA, United States Duration: 2006 Apr 18 → 2006 Apr 19 |
Publication series
| Name | Materials Research Society Symposium Proceedings |
|---|---|
| Volume | 913 |
| ISSN (Print) | 0272-9172 |
Other
| Other | 2006 MRS Spring Meeting |
|---|---|
| Country | United States |
| City | San Francisco, CA |
| Period | 06/4/18 → 06/4/19 |
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ASJC Scopus subject areas
- Materials Science(all)
- Condensed Matter Physics
- Mechanics of Materials
- Mechanical Engineering
Cite this
Quantum well nanopillar transistors. / Hu, Shu Fen; Sung, Chin Lung.
Transistor Scaling-Methods, Materials and Modeling. 2006. p. 85-92 (Materials Research Society Symposium Proceedings; Vol. 913).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Quantum well nanopillar transistors
AU - Hu, Shu Fen
AU - Sung, Chin Lung
PY - 2006/12/1
Y1 - 2006/12/1
N2 - We have fabricated vertical quantum well nanopillar transistors that consist of a vertical stack of coupled asymmetric quantum wells in a poly-silicon/ silicon nitride multilayer nano-pillars configuration with each well having a unique size. The devices consist of resonant tunneling in the poly-silicon/ silicon nitride stacked pillar material system surrounded by a Schottky gate. The gate electrode surrounds half side of a silicon pillar island, and the channel region exists at all the pillar silicon island. Current-voltage measurements at room temperature show prominent quantum effects due to electron resonance tunneling with side-gate. Accordingly, the vertical transistor offers high-shrinkage feature. By using the occupied area of the ULSI can be shrunk to 10% of that using conventional planar transistor. The small-occupied area leads to the small capacitance and the small load resistance, resulting in high speed and low power operation.
AB - We have fabricated vertical quantum well nanopillar transistors that consist of a vertical stack of coupled asymmetric quantum wells in a poly-silicon/ silicon nitride multilayer nano-pillars configuration with each well having a unique size. The devices consist of resonant tunneling in the poly-silicon/ silicon nitride stacked pillar material system surrounded by a Schottky gate. The gate electrode surrounds half side of a silicon pillar island, and the channel region exists at all the pillar silicon island. Current-voltage measurements at room temperature show prominent quantum effects due to electron resonance tunneling with side-gate. Accordingly, the vertical transistor offers high-shrinkage feature. By using the occupied area of the ULSI can be shrunk to 10% of that using conventional planar transistor. The small-occupied area leads to the small capacitance and the small load resistance, resulting in high speed and low power operation.
UR - http://www.scopus.com/inward/record.url?scp=33846045642&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33846045642&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:33846045642
SN - 1558998691
SN - 9781558998698
T3 - Materials Research Society Symposium Proceedings
SP - 85
EP - 92
BT - Transistor Scaling-Methods, Materials and Modeling
ER -