Quantum well nanopillar transistors

Shu Fen Hu, Chin Lung Sung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We have fabricated vertical quantum well nanopillar transistors that consist of a vertical stack of coupled asymmetric quantum wells in a poly-silicon/ silicon nitride multilayer nano-pillars configuration with each well having a unique size. The devices consist of resonant tunneling in the poly-silicon/ silicon nitride stacked pillar material system surrounded by a Schottky gate. The gate electrode surrounds half side of a silicon pillar island, and the channel region exists at all the pillar silicon island. Current-voltage measurements at room temperature show prominent quantum effects due to electron resonance tunneling with side-gate. Accordingly, the vertical transistor offers high-shrinkage feature. By using the occupied area of the ULSI can be shrunk to 10% of that using conventional planar transistor. The small-occupied area leads to the small capacitance and the small load resistance, resulting in high speed and low power operation.

Original languageEnglish
Title of host publicationTransistor Scaling-Methods, Materials and Modeling
Pages85-92
Number of pages8
Publication statusPublished - 2006 Dec 1
Event2006 MRS Spring Meeting - San Francisco, CA, United States
Duration: 2006 Apr 182006 Apr 19

Publication series

NameMaterials Research Society Symposium Proceedings
Volume913
ISSN (Print)0272-9172

Other

Other2006 MRS Spring Meeting
CountryUnited States
CitySan Francisco, CA
Period06/4/1806/4/19

Fingerprint

Silicon
Semiconductor quantum wells
Transistors
Silicon nitride
Electron resonance
Resonant tunneling
Voltage measurement
Electric current measurement
Multilayers
Capacitance
Electrodes
Temperature
silicon nitride

ASJC Scopus subject areas

  • Materials Science(all)
  • Condensed Matter Physics
  • Mechanics of Materials
  • Mechanical Engineering

Cite this

Hu, S. F., & Sung, C. L. (2006). Quantum well nanopillar transistors. In Transistor Scaling-Methods, Materials and Modeling (pp. 85-92). (Materials Research Society Symposium Proceedings; Vol. 913).

Quantum well nanopillar transistors. / Hu, Shu Fen; Sung, Chin Lung.

Transistor Scaling-Methods, Materials and Modeling. 2006. p. 85-92 (Materials Research Society Symposium Proceedings; Vol. 913).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hu, SF & Sung, CL 2006, Quantum well nanopillar transistors. in Transistor Scaling-Methods, Materials and Modeling. Materials Research Society Symposium Proceedings, vol. 913, pp. 85-92, 2006 MRS Spring Meeting, San Francisco, CA, United States, 06/4/18.
Hu SF, Sung CL. Quantum well nanopillar transistors. In Transistor Scaling-Methods, Materials and Modeling. 2006. p. 85-92. (Materials Research Society Symposium Proceedings).
Hu, Shu Fen ; Sung, Chin Lung. / Quantum well nanopillar transistors. Transistor Scaling-Methods, Materials and Modeling. 2006. pp. 85-92 (Materials Research Society Symposium Proceedings).
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