Program/erase speed and data retention trade-off in negative capacitance versatile memory

  • Chia Chi Fan
  • , Yu Chien Chiu
  • , Chien Liu
  • , Guan Lin Liou
  • , Wen Wei Lai
  • , Yi Ru Chen
  • , Tun Jen Chang
  • , Wan Hsin Chen
  • , Chun Hu Cheng*
  • , Chun Yen Chang
  • *Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

In this work, we investigated the performance tradeoff between program/erase speed and data retention of ferroelectric HfZrO memory. The monoclinic HfNO layer with a trapping mechanism was employed to improve the data retention. Under the thickness optimization of HfNO, the HfZrO/HfNO gate stack can be functionalized with volatile and non-volatile operation.

Original languageEnglish
Title of host publication2017 Silicon Nanoelectronics Workshop, SNW 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages101-102
Number of pages2
ISBN (Electronic)9784863486478
DOIs
Publication statusPublished - 2017 Dec 29
Event22nd Silicon Nanoelectronics Workshop, SNW 2017 - Kyoto, Japan
Duration: 2017 Jun 42017 Jun 5

Publication series

Name2017 Silicon Nanoelectronics Workshop, SNW 2017
Volume2017-January

Other

Other22nd Silicon Nanoelectronics Workshop, SNW 2017
Country/TerritoryJapan
CityKyoto
Period2017/06/042017/06/05

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Fingerprint

Dive into the research topics of 'Program/erase speed and data retention trade-off in negative capacitance versatile memory'. Together they form a unique fingerprint.

Cite this