Program/erase speed and data retention trade-off in negative capacitance versatile memory

Chia Chi Fan; Yu Chien Chiu; Chien Liu; Guan Lin Liou; Wen Wei Lai; Yi Ru Chen; Tun Jen Chang; Wan Hsin Chen; Chun Hu Cheng; Chun Yen Chang

doi:10.23919/SNW.2017.8242317

Program/erase speed and data retention trade-off in negative capacitance versatile memory

Chia Chi Fan, Yu Chien Chiu, Chien Liu, Guan Lin Liou, Wen Wei Lai, Yi Ru Chen, Tun Jen Chang, Wan Hsin Chen, Chun Hu Cheng^*, Chun Yen Chang

^*Corresponding author for this work

Department of Mechatronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

In this work, we investigated the performance tradeoff between program/erase speed and data retention of ferroelectric HfZrO memory. The monoclinic HfNO layer with a trapping mechanism was employed to improve the data retention. Under the thickness optimization of HfNO, the HfZrO/HfNO gate stack can be functionalized with volatile and non-volatile operation.

Original language	English
Title of host publication	2017 Silicon Nanoelectronics Workshop, SNW 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	101-102
Number of pages	2
ISBN (Electronic)	9784863486478
DOIs	https://doi.org/10.23919/SNW.2017.8242317
Publication status	Published - 2017 Dec 29
Event	22nd Silicon Nanoelectronics Workshop, SNW 2017 - Kyoto, Japan Duration: 2017 Jun 4 → 2017 Jun 5

Publication series

Name	2017 Silicon Nanoelectronics Workshop, SNW 2017
Volume	2017-January

Other

Other	22nd Silicon Nanoelectronics Workshop, SNW 2017
Country/Territory	Japan
City	Kyoto
Period	2017/06/04 → 2017/06/05

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

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10.23919/SNW.2017.8242317

Cite this

Fan, C. C., Chiu, Y. C., Liu, C., Liou, G. L., Lai, W. W., Chen, Y. R., Chang, T. J., Chen, W. H., Cheng, C. H., & Chang, C. Y. (2017). Program/erase speed and data retention trade-off in negative capacitance versatile memory. In 2017 Silicon Nanoelectronics Workshop, SNW 2017 (pp. 101-102). Article 8242317 (2017 Silicon Nanoelectronics Workshop, SNW 2017; Vol. 2017-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/SNW.2017.8242317

Program/erase speed and data retention trade-off in negative capacitance versatile memory. / Fan, Chia Chi; Chiu, Yu Chien; Liu, Chien et al.
2017 Silicon Nanoelectronics Workshop, SNW 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 101-102 8242317 (2017 Silicon Nanoelectronics Workshop, SNW 2017; Vol. 2017-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Fan, CC, Chiu, YC, Liu, C, Liou, GL, Lai, WW, Chen, YR, Chang, TJ, Chen, WH, Cheng, CH & Chang, CY 2017, Program/erase speed and data retention trade-off in negative capacitance versatile memory. in 2017 Silicon Nanoelectronics Workshop, SNW 2017., 8242317, 2017 Silicon Nanoelectronics Workshop, SNW 2017, vol. 2017-January, Institute of Electrical and Electronics Engineers Inc., pp. 101-102, 22nd Silicon Nanoelectronics Workshop, SNW 2017, Kyoto, Japan, 2017/06/04. https://doi.org/10.23919/SNW.2017.8242317

@inproceedings{cf876cb2bbd540b8b75a2f40dea5708d,

title = "Program/erase speed and data retention trade-off in negative capacitance versatile memory",

abstract = "In this work, we investigated the performance tradeoff between program/erase speed and data retention of ferroelectric HfZrO memory. The monoclinic HfNO layer with a trapping mechanism was employed to improve the data retention. Under the thickness optimization of HfNO, the HfZrO/HfNO gate stack can be functionalized with volatile and non-volatile operation.",

author = "Fan, {Chia Chi} and Chiu, {Yu Chien} and Chien Liu and Liou, {Guan Lin} and Lai, {Wen Wei} and Chen, {Yi Ru} and Chang, {Tun Jen} and Chen, {Wan Hsin} and Cheng, {Chun Hu} and Chang, {Chun Yen}",

note = "Publisher Copyright: {\textcopyright} 2017 JSAP.; 22nd Silicon Nanoelectronics Workshop, SNW 2017 ; Conference date: 04-06-2017 Through 05-06-2017",

year = "2017",

month = dec,

day = "29",

doi = "10.23919/SNW.2017.8242317",

language = "English",

series = "2017 Silicon Nanoelectronics Workshop, SNW 2017",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "101--102",

booktitle = "2017 Silicon Nanoelectronics Workshop, SNW 2017",

}

TY - GEN

T1 - Program/erase speed and data retention trade-off in negative capacitance versatile memory

AU - Fan, Chia Chi

AU - Chiu, Yu Chien

AU - Liu, Chien

AU - Liou, Guan Lin

AU - Lai, Wen Wei

AU - Chen, Yi Ru

AU - Chang, Tun Jen

AU - Chen, Wan Hsin

AU - Cheng, Chun Hu

AU - Chang, Chun Yen

PY - 2017/12/29

Y1 - 2017/12/29

N2 - In this work, we investigated the performance tradeoff between program/erase speed and data retention of ferroelectric HfZrO memory. The monoclinic HfNO layer with a trapping mechanism was employed to improve the data retention. Under the thickness optimization of HfNO, the HfZrO/HfNO gate stack can be functionalized with volatile and non-volatile operation.

AB - In this work, we investigated the performance tradeoff between program/erase speed and data retention of ferroelectric HfZrO memory. The monoclinic HfNO layer with a trapping mechanism was employed to improve the data retention. Under the thickness optimization of HfNO, the HfZrO/HfNO gate stack can be functionalized with volatile and non-volatile operation.

UR - http://www.scopus.com/inward/record.url?scp=85051013076&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85051013076&partnerID=8YFLogxK

U2 - 10.23919/SNW.2017.8242317

DO - 10.23919/SNW.2017.8242317

M3 - Conference contribution

AN - SCOPUS:85051013076

T3 - 2017 Silicon Nanoelectronics Workshop, SNW 2017

SP - 101

EP - 102

BT - 2017 Silicon Nanoelectronics Workshop, SNW 2017

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 22nd Silicon Nanoelectronics Workshop, SNW 2017

Y2 - 4 June 2017 through 5 June 2017

ER -

Program/erase speed and data retention trade-off in negative capacitance versatile memory

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