Program/erase speed and data retention trade-off in negative capacitance versatile memory

Chia Chi Fan, Yu Chien Chiu, Chien Liu, Guan Lin Liou, Wen Wei Lai, Yi Ru Chen, Tun Jen Chang, Wan Hsin Chen, Chun-Hu Cheng, Chun Yen Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this work, we investigated the performance tradeoff between program/erase speed and data retention of ferroelectric HfZrO memory. The monoclinic HfNO layer with a trapping mechanism was employed to improve the data retention. Under the thickness optimization of HfNO, the HfZrO/HfNO gate stack can be functionalized with volatile and non-volatile operation.

Original languageEnglish
Title of host publication2017 Silicon Nanoelectronics Workshop, SNW 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages101-102
Number of pages2
ISBN (Electronic)9784863486478
DOIs
Publication statusPublished - 2017 Dec 29
Event22nd Silicon Nanoelectronics Workshop, SNW 2017 - Kyoto, Japan
Duration: 2017 Jun 42017 Jun 5

Publication series

Name2017 Silicon Nanoelectronics Workshop, SNW 2017
Volume2017-January

Other

Other22nd Silicon Nanoelectronics Workshop, SNW 2017
CountryJapan
CityKyoto
Period17/6/417/6/5

Fingerprint

Ferroelectric materials
Capacitance
Data storage equipment

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Fan, C. C., Chiu, Y. C., Liu, C., Liou, G. L., Lai, W. W., Chen, Y. R., ... Chang, C. Y. (2017). Program/erase speed and data retention trade-off in negative capacitance versatile memory. In 2017 Silicon Nanoelectronics Workshop, SNW 2017 (pp. 101-102). [8242317] (2017 Silicon Nanoelectronics Workshop, SNW 2017; Vol. 2017-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/SNW.2017.8242317

Program/erase speed and data retention trade-off in negative capacitance versatile memory. / Fan, Chia Chi; Chiu, Yu Chien; Liu, Chien; Liou, Guan Lin; Lai, Wen Wei; Chen, Yi Ru; Chang, Tun Jen; Chen, Wan Hsin; Cheng, Chun-Hu; Chang, Chun Yen.

2017 Silicon Nanoelectronics Workshop, SNW 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 101-102 8242317 (2017 Silicon Nanoelectronics Workshop, SNW 2017; Vol. 2017-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Fan, CC, Chiu, YC, Liu, C, Liou, GL, Lai, WW, Chen, YR, Chang, TJ, Chen, WH, Cheng, C-H & Chang, CY 2017, Program/erase speed and data retention trade-off in negative capacitance versatile memory. in 2017 Silicon Nanoelectronics Workshop, SNW 2017., 8242317, 2017 Silicon Nanoelectronics Workshop, SNW 2017, vol. 2017-January, Institute of Electrical and Electronics Engineers Inc., pp. 101-102, 22nd Silicon Nanoelectronics Workshop, SNW 2017, Kyoto, Japan, 17/6/4. https://doi.org/10.23919/SNW.2017.8242317
Fan CC, Chiu YC, Liu C, Liou GL, Lai WW, Chen YR et al. Program/erase speed and data retention trade-off in negative capacitance versatile memory. In 2017 Silicon Nanoelectronics Workshop, SNW 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 101-102. 8242317. (2017 Silicon Nanoelectronics Workshop, SNW 2017). https://doi.org/10.23919/SNW.2017.8242317
Fan, Chia Chi ; Chiu, Yu Chien ; Liu, Chien ; Liou, Guan Lin ; Lai, Wen Wei ; Chen, Yi Ru ; Chang, Tun Jen ; Chen, Wan Hsin ; Cheng, Chun-Hu ; Chang, Chun Yen. / Program/erase speed and data retention trade-off in negative capacitance versatile memory. 2017 Silicon Nanoelectronics Workshop, SNW 2017. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 101-102 (2017 Silicon Nanoelectronics Workshop, SNW 2017).
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