TY - GEN
T1 - Parallel pipelined histogram architecture via C-slow retiming
AU - Cadenas, Jose O.
AU - Sherratt, R. Simon
AU - Huerta, Pablo
AU - Kao, Wen Chung
AU - Megson, Graham
PY - 2013
Y1 - 2013
N2 - A parallel pipelined array of cells suitable for realtime computation of histograms is proposed. The cell architecture builds on previous work to now allow operating on a stream of data at 1 pixel per clock cycle. This new cell is more suitable for interfacing to camera sensors or to microprocessors of 8-bit data buses which are common in consumer digital cameras. Arrays using the new proposed cells are obtained via C-slow retiming techniques and can be clocked at a 65% faster frequency than previous arrays. This achieves over 80% of the performance of two-pixel per clock cycle parallel pipelined arrays.
AB - A parallel pipelined array of cells suitable for realtime computation of histograms is proposed. The cell architecture builds on previous work to now allow operating on a stream of data at 1 pixel per clock cycle. This new cell is more suitable for interfacing to camera sensors or to microprocessors of 8-bit data buses which are common in consumer digital cameras. Arrays using the new proposed cells are obtained via C-slow retiming techniques and can be clocked at a 65% faster frequency than previous arrays. This achieves over 80% of the performance of two-pixel per clock cycle parallel pipelined arrays.
UR - http://www.scopus.com/inward/record.url?scp=84876373414&partnerID=8YFLogxK
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U2 - 10.1109/ICCE.2013.6486871
DO - 10.1109/ICCE.2013.6486871
M3 - Conference contribution
AN - SCOPUS:84876373414
SN - 9781467313612
T3 - Digest of Technical Papers - IEEE International Conference on Consumer Electronics
SP - 230
EP - 231
BT - 2013 IEEE International Conference on Consumer Electronics, ICCE 2013
T2 - 2013 IEEE International Conference on Consumer Electronics, ICCE 2013
Y2 - 11 January 2013 through 14 January 2013
ER -