Parallel pipelined histogram architecture via C-slow retiming

Jose O. Cadenas, R. Simon Sherratt, Pablo Huerta, Wen-Chung Kao, Graham Megson

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A parallel pipelined array of cells suitable for realtime computation of histograms is proposed. The cell architecture builds on previous work to now allow operating on a stream of data at 1 pixel per clock cycle. This new cell is more suitable for interfacing to camera sensors or to microprocessors of 8-bit data buses which are common in consumer digital cameras. Arrays using the new proposed cells are obtained via C-slow retiming techniques and can be clocked at a 65% faster frequency than previous arrays. This achieves over 80% of the performance of two-pixel per clock cycle parallel pipelined arrays.

Original languageEnglish
Title of host publication2013 IEEE International Conference on Consumer Electronics, ICCE 2013
Pages230-231
Number of pages2
DOIs
Publication statusPublished - 2013 Apr 24
Event2013 IEEE International Conference on Consumer Electronics, ICCE 2013 - Las Vegas, NV, United States
Duration: 2013 Jan 112013 Jan 14

Publication series

NameDigest of Technical Papers - IEEE International Conference on Consumer Electronics
ISSN (Print)0747-668X

Other

Other2013 IEEE International Conference on Consumer Electronics, ICCE 2013
CountryUnited States
CityLas Vegas, NV
Period13/1/1113/1/14

Fingerprint

Clocks
Pixels
Digital cameras
Microprocessor chips
Cameras
Sensors

ASJC Scopus subject areas

  • Industrial and Manufacturing Engineering
  • Electrical and Electronic Engineering

Cite this

Cadenas, J. O., Sherratt, R. S., Huerta, P., Kao, W-C., & Megson, G. (2013). Parallel pipelined histogram architecture via C-slow retiming. In 2013 IEEE International Conference on Consumer Electronics, ICCE 2013 (pp. 230-231). [6486871] (Digest of Technical Papers - IEEE International Conference on Consumer Electronics). https://doi.org/10.1109/ICCE.2013.6486871

Parallel pipelined histogram architecture via C-slow retiming. / Cadenas, Jose O.; Sherratt, R. Simon; Huerta, Pablo; Kao, Wen-Chung; Megson, Graham.

2013 IEEE International Conference on Consumer Electronics, ICCE 2013. 2013. p. 230-231 6486871 (Digest of Technical Papers - IEEE International Conference on Consumer Electronics).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cadenas, JO, Sherratt, RS, Huerta, P, Kao, W-C & Megson, G 2013, Parallel pipelined histogram architecture via C-slow retiming. in 2013 IEEE International Conference on Consumer Electronics, ICCE 2013., 6486871, Digest of Technical Papers - IEEE International Conference on Consumer Electronics, pp. 230-231, 2013 IEEE International Conference on Consumer Electronics, ICCE 2013, Las Vegas, NV, United States, 13/1/11. https://doi.org/10.1109/ICCE.2013.6486871
Cadenas JO, Sherratt RS, Huerta P, Kao W-C, Megson G. Parallel pipelined histogram architecture via C-slow retiming. In 2013 IEEE International Conference on Consumer Electronics, ICCE 2013. 2013. p. 230-231. 6486871. (Digest of Technical Papers - IEEE International Conference on Consumer Electronics). https://doi.org/10.1109/ICCE.2013.6486871
Cadenas, Jose O. ; Sherratt, R. Simon ; Huerta, Pablo ; Kao, Wen-Chung ; Megson, Graham. / Parallel pipelined histogram architecture via C-slow retiming. 2013 IEEE International Conference on Consumer Electronics, ICCE 2013. 2013. pp. 230-231 (Digest of Technical Papers - IEEE International Conference on Consumer Electronics).
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