Parallel pipelined array architectures for real-time histogram computation in consumer devices

José O. Cadenas*, R. Simon Sherratt, Pablo Huerta, Wen Chung Kao

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

12 Citations (Scopus)


The real-time parallel computation of histograms using an array of pipelined cells is proposed and prototyped in this paper with application to consumer imaging products. The array operates in two modes: histogram computation and histogram reading. The proposed parallel computation method does not use any memory blocks. The resulting histogram bins can be stored into an external memory block in a pipelined fashion for subsequent reading or streaming of the results. The array of cells can be tuned to accommodate the required data path width in a VLSI image processing engine as present in many imaging consumer devices. Synthesis of the architectures presented in this paper in FPGA are shown to compute the real-time histogram of images streamed at over 36 megapixels at 30 frames/s by processing in parallel 1, 2 or 4 pixels per clock cycle 1.

Original languageEnglish
Article number6131111
Pages (from-to)1460-1464
Number of pages5
JournalIEEE Transactions on Consumer Electronics
Issue number4
Publication statusPublished - 2011 Nov


  • FPGA
  • Parallel histograms
  • digital imaging
  • image processing
  • pipelined array

ASJC Scopus subject areas

  • Media Technology
  • Electrical and Electronic Engineering


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