Parallel computing architecture for eye tracking systems

Wen Chung Kao, Jui Che Tsai, Yi Chin Chiu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

It has been proved that visible light gaze trackers (VLGT) outperforms the traditional infra-ray based ones with respect to user experience. Still, the computational complexity of analyzing eye images becomes considerably higher due to the fact that the algorithm should accommodate various illumination conditions. In this paper, we propose a parallel computing architecture for realizing a high precision algorithm on multi-core microprocessor. The experimental result shows the proposed architecture could be applied to the design of a high speed VLGT with frame rate higher than 700 frames/s.

Original languageEnglish
Title of host publication2017 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages289-290
Number of pages2
ISBN (Electronic)9781509040179
DOIs
Publication statusPublished - 2017 Jul 25
Event4th IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2017 - Taipei, United States
Duration: 2017 Jun 122017 Jun 14

Publication series

Name2017 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2017

Other

Other4th IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2017
CountryUnited States
CityTaipei
Period17/6/1217/6/14

Fingerprint

Parallel processing systems
microprocessors
Microprocessor chips
Computational complexity
rays
Lighting
illumination
high speed

ASJC Scopus subject areas

  • Computer Vision and Pattern Recognition
  • Computer Networks and Communications
  • Signal Processing
  • Biomedical Engineering
  • Instrumentation
  • Electrical and Electronic Engineering

Cite this

Kao, W. C., Tsai, J. C., & Chiu, Y. C. (2017). Parallel computing architecture for eye tracking systems. In 2017 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2017 (pp. 289-290). [7991109] (2017 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCE-China.2017.7991109

Parallel computing architecture for eye tracking systems. / Kao, Wen Chung; Tsai, Jui Che; Chiu, Yi Chin.

2017 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 289-290 7991109 (2017 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2017).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kao, WC, Tsai, JC & Chiu, YC 2017, Parallel computing architecture for eye tracking systems. in 2017 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2017., 7991109, 2017 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2017, Institute of Electrical and Electronics Engineers Inc., pp. 289-290, 4th IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2017, Taipei, United States, 17/6/12. https://doi.org/10.1109/ICCE-China.2017.7991109
Kao WC, Tsai JC, Chiu YC. Parallel computing architecture for eye tracking systems. In 2017 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 289-290. 7991109. (2017 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2017). https://doi.org/10.1109/ICCE-China.2017.7991109
Kao, Wen Chung ; Tsai, Jui Che ; Chiu, Yi Chin. / Parallel computing architecture for eye tracking systems. 2017 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2017. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 289-290 (2017 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2017).
@inproceedings{c7482e7b590a4b3c8e973ce427ee2326,
title = "Parallel computing architecture for eye tracking systems",
abstract = "It has been proved that visible light gaze trackers (VLGT) outperforms the traditional infra-ray based ones with respect to user experience. Still, the computational complexity of analyzing eye images becomes considerably higher due to the fact that the algorithm should accommodate various illumination conditions. In this paper, we propose a parallel computing architecture for realizing a high precision algorithm on multi-core microprocessor. The experimental result shows the proposed architecture could be applied to the design of a high speed VLGT with frame rate higher than 700 frames/s.",
author = "Kao, {Wen Chung} and Tsai, {Jui Che} and Chiu, {Yi Chin}",
year = "2017",
month = "7",
day = "25",
doi = "10.1109/ICCE-China.2017.7991109",
language = "English",
series = "2017 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2017",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "289--290",
booktitle = "2017 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2017",

}

TY - GEN

T1 - Parallel computing architecture for eye tracking systems

AU - Kao, Wen Chung

AU - Tsai, Jui Che

AU - Chiu, Yi Chin

PY - 2017/7/25

Y1 - 2017/7/25

N2 - It has been proved that visible light gaze trackers (VLGT) outperforms the traditional infra-ray based ones with respect to user experience. Still, the computational complexity of analyzing eye images becomes considerably higher due to the fact that the algorithm should accommodate various illumination conditions. In this paper, we propose a parallel computing architecture for realizing a high precision algorithm on multi-core microprocessor. The experimental result shows the proposed architecture could be applied to the design of a high speed VLGT with frame rate higher than 700 frames/s.

AB - It has been proved that visible light gaze trackers (VLGT) outperforms the traditional infra-ray based ones with respect to user experience. Still, the computational complexity of analyzing eye images becomes considerably higher due to the fact that the algorithm should accommodate various illumination conditions. In this paper, we propose a parallel computing architecture for realizing a high precision algorithm on multi-core microprocessor. The experimental result shows the proposed architecture could be applied to the design of a high speed VLGT with frame rate higher than 700 frames/s.

UR - http://www.scopus.com/inward/record.url?scp=85028512763&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85028512763&partnerID=8YFLogxK

U2 - 10.1109/ICCE-China.2017.7991109

DO - 10.1109/ICCE-China.2017.7991109

M3 - Conference contribution

AN - SCOPUS:85028512763

T3 - 2017 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2017

SP - 289

EP - 290

BT - 2017 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2017

PB - Institute of Electrical and Electronics Engineers Inc.

ER -