TY - JOUR
T1 - Overview on ESD protection designs of low-parasitic capacitance for RF ICs in CMOS technologies
AU - Ker, Ming Dou
AU - Lin, Chun Yu
AU - Hsiao, Yuan Wen
N1 - Funding Information:
Manuscript received May 18, 2010; revised November 10, 2010; accepted January 5, 2011. Date of publication January 13, 2011; date of current version June 15, 2011. This work was supported by National Science Council, Taiwan, under Contract NSC 98-2221-E-009-113-MY2; by Ministry of Economic Affairs, Taiwan, under Grant 99-EC-17-A-01-S1-104; and by the “Aim for the Top University Plan” of National Chiao-Tung University and Ministry of Education, Taiwan.
PY - 2011/6
Y1 - 2011/6
N2 - CMOS technology has been widely used to implement radio-frequency integrated circuits (RF ICs). However, the thinner gate oxide in nanoscale CMOS technology seriously degrades the electrostatic discharge (ESD) robustness of RF ICs. Therefore, on-chip ESD protection designs must be added at all input/output pads in RF circuits against ESD damages. To minimize the impacts from ESD protection circuit on RF performances, ESD protection circuit at input/output pads must be carefully designed. An overview on ESD protection designs with low parasitic capacitance for RF circuits in CMOS technology is presented in this paper. The comparisons among these ESD protection designs are also discussed. With the reduced parasitic capacitance, ESD protection circuit can be easily combined or co-designed with RF circuits. As the operating frequencies of RF circuits increase, on-chip ESD protection designs for RF applications will continuously be an important design task.
AB - CMOS technology has been widely used to implement radio-frequency integrated circuits (RF ICs). However, the thinner gate oxide in nanoscale CMOS technology seriously degrades the electrostatic discharge (ESD) robustness of RF ICs. Therefore, on-chip ESD protection designs must be added at all input/output pads in RF circuits against ESD damages. To minimize the impacts from ESD protection circuit on RF performances, ESD protection circuit at input/output pads must be carefully designed. An overview on ESD protection designs with low parasitic capacitance for RF circuits in CMOS technology is presented in this paper. The comparisons among these ESD protection designs are also discussed. With the reduced parasitic capacitance, ESD protection circuit can be easily combined or co-designed with RF circuits. As the operating frequencies of RF circuits increase, on-chip ESD protection designs for RF applications will continuously be an important design task.
KW - ESD protection circuits
KW - Electrostatic discharge (ESD)
KW - low capacitance
KW - radio-frequency integrated circuit (RF IC)
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U2 - 10.1109/TDMR.2011.2106129
DO - 10.1109/TDMR.2011.2106129
M3 - Review article
AN - SCOPUS:79959532017
SN - 1530-4388
VL - 11
SP - 207
EP - 218
JO - IEEE Transactions on Device and Materials Reliability
JF - IEEE Transactions on Device and Materials Reliability
IS - 2
M1 - 5688227
ER -