Optimization on layout style of diode stackup for on-chip ESD protection

Chun Yu Lin, Mei Lian Fan

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

The diode stackup has been used as on-chip electrostatic discharge (ESD) protection for some applications in which the input/output signal swing is higher than VDD or lower than VSS. A novel ESD protection structure of diode stackup is proposed for effective on-chip ESD protection. Experimental results in 65-nm CMOS process show that the optimization on layout style can improve the ESD robustness, decrease the turn-on resistance, and lessen the parasitic capacitance of the diode stackup.

Original languageEnglish
Article number6763105
Pages (from-to)775-777
Number of pages3
JournalIEEE Transactions on Device and Materials Reliability
Volume14
Issue number2
DOIs
Publication statusPublished - 2014

Fingerprint

Electrostatic discharge
Diodes
Capacitance

Keywords

  • Diode
  • electrostatic discharge (ESD)
  • layout
  • stackup

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Safety, Risk, Reliability and Quality

Cite this

Optimization on layout style of diode stackup for on-chip ESD protection. / Lin, Chun Yu; Fan, Mei Lian.

In: IEEE Transactions on Device and Materials Reliability, Vol. 14, No. 2, 6763105, 2014, p. 775-777.

Research output: Contribution to journalArticle

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