Abstract
Regular expressions are widely used in the network intrusion detection system (NIDS) to represent attack patterns. Previously, many hardware architectures have been proposed to accelerate regular expression matching using field-programmable gate array (FPGA) because FPGAs allow updating of new attack patterns. Because of the increasing number of attacks, we need to accommodate a large number of regular expressions on FPGAs. Although the minimization of logic equations has been studied intensively in the area of computer-aided design (CAD), the minimization of multiple regular expressions has been largely neglected. This paper presents a novel sharing architecture allowing our algorithm to extract and share common subregular expressions. Experimental results show that our sharing scheme significantly reduces the area of pattern matching circuits for regular expression.
Original language | English |
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Pages (from-to) | 1303-1310 |
Number of pages | 8 |
Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Volume | 15 |
Issue number | 12 |
DOIs | |
Publication status | Published - 2007 Dec |
Externally published | Yes |
Keywords
- Field-programmable gate array (FPGA)
- Finite automata
- Intrusion detection
- Pattern matching
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering