TY - GEN
T1 - One-Transistor ferroelectric versatile memory
T2 - 36th IEEE Symposium on VLSI Technology, VLSI Technology 2016
AU - Chiu, Yu Chien
AU - Cheng, Chun Hu
AU - Chang, Chun Yen
AU - Tang, Ying Tsan
AU - Chen, Min Cheng
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/9/21
Y1 - 2016/9/21
N2 - In this work, we report a ferroelectric versatile memory (FE-VM) with strained-gate engineering. The memory window of high strain case was improved by ∼47% at the same ferroelectric thickness, which agrees with the increase of orthorhombic crystallinity. Based on a reliable first principle calculation (FPC), we clarify that the gate strain accelerates the phase transformation from metastable monoclinic to orthorhombic and thus largely enhances the ferroelectric polarization without increasing dielectric thickness. On the other hand, the orthorhombic FE-AFE phase transition plays a key role in realizing negative capacitance (NC) effect at high gate electric field. This 1T strained-gate FE-VM with ferroelectric NC achieves a sub-60-mVdec subthreshold swing (SS) over ∼4 decade of ID to provide a 1∼10 fA/μm Ioff and >108 Ion/Ioff ratio, which allows for a fast 20-ns P/E switching during 1012 cycling endurance.
AB - In this work, we report a ferroelectric versatile memory (FE-VM) with strained-gate engineering. The memory window of high strain case was improved by ∼47% at the same ferroelectric thickness, which agrees with the increase of orthorhombic crystallinity. Based on a reliable first principle calculation (FPC), we clarify that the gate strain accelerates the phase transformation from metastable monoclinic to orthorhombic and thus largely enhances the ferroelectric polarization without increasing dielectric thickness. On the other hand, the orthorhombic FE-AFE phase transition plays a key role in realizing negative capacitance (NC) effect at high gate electric field. This 1T strained-gate FE-VM with ferroelectric NC achieves a sub-60-mVdec subthreshold swing (SS) over ∼4 decade of ID to provide a 1∼10 fA/μm Ioff and >108 Ion/Ioff ratio, which allows for a fast 20-ns P/E switching during 1012 cycling endurance.
UR - http://www.scopus.com/inward/record.url?scp=84990923862&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84990923862&partnerID=8YFLogxK
U2 - 10.1109/VLSIT.2016.7573414
DO - 10.1109/VLSIT.2016.7573414
M3 - Conference contribution
AN - SCOPUS:84990923862
T3 - Digest of Technical Papers - Symposium on VLSI Technology
BT - 2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 13 June 2016 through 16 June 2016
ER -