On-Chip ESD Protection Device for High-Speed I/O Applications in CMOS Technology

Jie Ting Chen, Chun Yu Lin, Ming Dou Ker*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

28 Citations (Scopus)


The diode operated under forward-biased condition has been widely used as an on-chip electrostatic discharge (ESD) protection device for high-speed circuits to sustain high ESD robustness, but the parasitic capacitance of diode may bring a negative impact to the circuits operating at higher speed. The ESD protection design with low parasitic capacitance has been strongly requested in high-speed I/O applications. The traditional methods to reduce parasitic capacitance were using a stacked diode or a stacked diode with embedded silicon-controlled rectifier (SCR). The stacked diode or the stacked diode with embedded SCR would have larger turn-on resistance to cause a higher clamping voltage. It should be further improved to achieve good ESD protection effectiveness for the high-speed I/O applications. In this paper, a new ESD protection device with reduced parasitic capacitance and smaller turn-on resistance to improve ESD protection effectiveness is proposed. The measurement results from the silicon chip have demonstrated that the proposed ESD device can achieve smaller parasitic capacitance, lower turn-on resistance, and higher ESD robustness, compared with the conventional devices. The proposed ESD protection device is very suitable to protect the high-speed I/O circuits in nanoscale CMOS technology.

Original languageEnglish
Article number8008837
Pages (from-to)3979-3985
Number of pages7
JournalIEEE Transactions on Electron Devices
Issue number10
Publication statusPublished - 2017 Oct


  • Diode
  • ESD protection
  • Electrostatic discharge (ESD)
  • High-speed I/O
  • Silicon-controlled rectifier (SCR)

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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