On-chip ESD protection designs in RF integrated circuits for radio and wireless applications

Ming Dou Ker; Chun Yu Lin

doi:10.1109/EDSSC.2013.6628166

On-chip ESD protection designs in RF integrated circuits for radio and wireless applications

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

CMOS technology has been used to implement the radio and wireless integrated circuits. However, the thinner gate oxide in nanoscale CMOS technology seriously degrades the electrostatic discharge (ESD) robustness. Therefore, on-chip ESD protection designs must be added at all input/output pads in CMOS chip. To minimize the impacts from ESD protection design on circuit performances, ESD protection at input/output pads must be carefully designed. A review on ESD protection designs with low parasitic capacitance for radio and wireless applications is presented in this paper. The comparisons among these ESD protection designs are also discussed.

Original language	English
Title of host publication	2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013
DOIs	https://doi.org/10.1109/EDSSC.2013.6628166
Publication status	Published - 2013
Externally published	Yes
Event	2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013 - Hong Kong, Hong Kong Duration: 2013 Jun 3 → 2013 Jun 5

Publication series

Name	2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013

Other

Other	2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013
Country/Territory	Hong Kong
City	Hong Kong
Period	2013/06/03 → 2013/06/05

Keywords

Electrostatic discharge (ESD)
low capacitance
radio-frequency (RF)

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/EDSSC.2013.6628166

Cite this

Ker, M. D., & Lin, C. Y. (2013). On-chip ESD protection designs in RF integrated circuits for radio and wireless applications. In 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013 Article 6628166 (2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013). https://doi.org/10.1109/EDSSC.2013.6628166

On-chip ESD protection designs in RF integrated circuits for radio and wireless applications. / Ker, Ming Dou; Lin, Chun Yu.
2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013. 2013. 6628166 (2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ker, MD & Lin, CY 2013, On-chip ESD protection designs in RF integrated circuits for radio and wireless applications. in 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013., 6628166, 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013, 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013, Hong Kong, Hong Kong, 2013/06/03. https://doi.org/10.1109/EDSSC.2013.6628166

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AB - CMOS technology has been used to implement the radio and wireless integrated circuits. However, the thinner gate oxide in nanoscale CMOS technology seriously degrades the electrostatic discharge (ESD) robustness. Therefore, on-chip ESD protection designs must be added at all input/output pads in CMOS chip. To minimize the impacts from ESD protection design on circuit performances, ESD protection at input/output pads must be carefully designed. A review on ESD protection designs with low parasitic capacitance for radio and wireless applications is presented in this paper. The comparisons among these ESD protection designs are also discussed.

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On-chip ESD protection designs in RF integrated circuits for radio and wireless applications

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Keywords

ASJC Scopus subject areas

Access to Document

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