On-chip ESD protection designs in RF integrated circuits for radio and wireless applications

Ming Dou Ker, Chun-Yu Lin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

CMOS technology has been used to implement the radio and wireless integrated circuits. However, the thinner gate oxide in nanoscale CMOS technology seriously degrades the electrostatic discharge (ESD) robustness. Therefore, on-chip ESD protection designs must be added at all input/output pads in CMOS chip. To minimize the impacts from ESD protection design on circuit performances, ESD protection at input/output pads must be carefully designed. A review on ESD protection designs with low parasitic capacitance for radio and wireless applications is presented in this paper. The comparisons among these ESD protection designs are also discussed.

Original languageEnglish
Title of host publication2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013
DOIs
Publication statusPublished - 2013 Dec 23
Event2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013 - Hong Kong, Hong Kong
Duration: 2013 Jun 32013 Jun 5

Publication series

Name2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013

Other

Other2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013
CountryHong Kong
CityHong Kong
Period13/6/313/6/5

Fingerprint

Electrostatic discharge
Integrated circuits
Capacitance
Oxides
Networks (circuits)

Keywords

  • Electrostatic discharge (ESD)
  • low capacitance
  • radio-frequency (RF)

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Ker, M. D., & Lin, C-Y. (2013). On-chip ESD protection designs in RF integrated circuits for radio and wireless applications. In 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013 [6628166] (2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013). https://doi.org/10.1109/EDSSC.2013.6628166

On-chip ESD protection designs in RF integrated circuits for radio and wireless applications. / Ker, Ming Dou; Lin, Chun-Yu.

2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013. 2013. 6628166 (2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ker, MD & Lin, C-Y 2013, On-chip ESD protection designs in RF integrated circuits for radio and wireless applications. in 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013., 6628166, 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013, 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013, Hong Kong, Hong Kong, 13/6/3. https://doi.org/10.1109/EDSSC.2013.6628166
Ker MD, Lin C-Y. On-chip ESD protection designs in RF integrated circuits for radio and wireless applications. In 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013. 2013. 6628166. (2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013). https://doi.org/10.1109/EDSSC.2013.6628166
Ker, Ming Dou ; Lin, Chun-Yu. / On-chip ESD protection designs in RF integrated circuits for radio and wireless applications. 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013. 2013. (2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013).
@inproceedings{49765c89bdc0438f8a2430ce6692ad75,
title = "On-chip ESD protection designs in RF integrated circuits for radio and wireless applications",
abstract = "CMOS technology has been used to implement the radio and wireless integrated circuits. However, the thinner gate oxide in nanoscale CMOS technology seriously degrades the electrostatic discharge (ESD) robustness. Therefore, on-chip ESD protection designs must be added at all input/output pads in CMOS chip. To minimize the impacts from ESD protection design on circuit performances, ESD protection at input/output pads must be carefully designed. A review on ESD protection designs with low parasitic capacitance for radio and wireless applications is presented in this paper. The comparisons among these ESD protection designs are also discussed.",
keywords = "Electrostatic discharge (ESD), low capacitance, radio-frequency (RF)",
author = "Ker, {Ming Dou} and Chun-Yu Lin",
year = "2013",
month = "12",
day = "23",
doi = "10.1109/EDSSC.2013.6628166",
language = "English",
isbn = "9781467325233",
series = "2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013",
booktitle = "2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013",

}

TY - GEN

T1 - On-chip ESD protection designs in RF integrated circuits for radio and wireless applications

AU - Ker, Ming Dou

AU - Lin, Chun-Yu

PY - 2013/12/23

Y1 - 2013/12/23

N2 - CMOS technology has been used to implement the radio and wireless integrated circuits. However, the thinner gate oxide in nanoscale CMOS technology seriously degrades the electrostatic discharge (ESD) robustness. Therefore, on-chip ESD protection designs must be added at all input/output pads in CMOS chip. To minimize the impacts from ESD protection design on circuit performances, ESD protection at input/output pads must be carefully designed. A review on ESD protection designs with low parasitic capacitance for radio and wireless applications is presented in this paper. The comparisons among these ESD protection designs are also discussed.

AB - CMOS technology has been used to implement the radio and wireless integrated circuits. However, the thinner gate oxide in nanoscale CMOS technology seriously degrades the electrostatic discharge (ESD) robustness. Therefore, on-chip ESD protection designs must be added at all input/output pads in CMOS chip. To minimize the impacts from ESD protection design on circuit performances, ESD protection at input/output pads must be carefully designed. A review on ESD protection designs with low parasitic capacitance for radio and wireless applications is presented in this paper. The comparisons among these ESD protection designs are also discussed.

KW - Electrostatic discharge (ESD)

KW - low capacitance

KW - radio-frequency (RF)

UR - http://www.scopus.com/inward/record.url?scp=84890499289&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84890499289&partnerID=8YFLogxK

U2 - 10.1109/EDSSC.2013.6628166

DO - 10.1109/EDSSC.2013.6628166

M3 - Conference contribution

AN - SCOPUS:84890499289

SN - 9781467325233

T3 - 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013

BT - 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013

ER -