Numerical confirmation of inelastic trap-assisted tunneling (ITAT) as SILC mechanism

Ting Kuo Kang*, Ming Jer Chen, Chuan Hsi Liu, Yih J. Chang, Shou Kong Fan

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

12 Citations (Scopus)


This paper presents a quite comprehensive procedure covering both the stress-induced leakage current (SILC) and oxide breakdown, achieved by balancing systematically the modeling and experimental works. The underlying model as quoted in the literature features three key parameters: the tunneling relaxation time τ, the neutral electron trap density Nt, and the trap energy level Et. First of all, 7-nm thick oxide MOS devices with wide range oxide areas are throughly characterized in terms of the optically induced trap filling, the charge-to-breakdown statistics, the gate voltage developments with the time, and the SILC I-V. The former three are involved together with a percolation oxide breakdown model to build Nt explicitly as function of the stress electron fluence. Then the overall tunneling probability is calculated with which a best fitting to SILC I-V furnishes τ of 4.0 × 10-13 s and Et of 3.4 eV. The extracted τ is found to match exactly that extrapolated from existing data. Such striking consistencies thereby provide evidence that inelastic trap-assisted tunneling (ITAT) is indeed the SILC mechanism. Differences and similarities of the involved physical parameters between different studies are compared as well.

Original languageEnglish
Pages (from-to)2317-2322
Number of pages6
JournalIEEE Transactions on Electron Devices
Issue number10
Publication statusPublished - 2001 Oct
Externally publishedYes


  • Flash
  • Gated-diode
  • Inelastic tunneling
  • Oxide breakdown
  • Percolation
  • SILC
  • Stress-induced leakage current
  • Trap-assisted tunneling

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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