Abstract
This paper presents a quite comprehensive procedure covering both the stress-induced leakage current (SILC) and oxide breakdown, achieved by balancing systematically the modeling and experimental works. The underlying model as quoted in the literature features three key parameters: the tunneling relaxation time τ, the neutral electron trap density Nt, and the trap energy level Et. First of all, 7-nm thick oxide MOS devices with wide range oxide areas are throughly characterized in terms of the optically induced trap filling, the charge-to-breakdown statistics, the gate voltage developments with the time, and the SILC I-V. The former three are involved together with a percolation oxide breakdown model to build Nt explicitly as function of the stress electron fluence. Then the overall tunneling probability is calculated with which a best fitting to SILC I-V furnishes τ of 4.0 × 10-13 s and Et of 3.4 eV. The extracted τ is found to match exactly that extrapolated from existing data. Such striking consistencies thereby provide evidence that inelastic trap-assisted tunneling (ITAT) is indeed the SILC mechanism. Differences and similarities of the involved physical parameters between different studies are compared as well.
| Original language | English |
|---|---|
| Pages (from-to) | 2317-2322 |
| Number of pages | 6 |
| Journal | IEEE Transactions on Electron Devices |
| Volume | 48 |
| Issue number | 10 |
| DOIs | |
| Publication status | Published - 2001 Oct 1 |
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Keywords
- Flash
- Gated-diode
- Inelastic tunneling
- MOSFET
- Oxide breakdown
- Percolation
- SILC
- Stress-induced leakage current
- Trap-assisted tunneling
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
Cite this
Numerical confirmation of inelastic trap-assisted tunneling (ITAT) as SILC mechanism. / Kang, Ting Kuo; Chen, Ming Jer; Liu, Chuan Hsi; Chang, Yih J.; Fan, Shou Kong.
In: IEEE Transactions on Electron Devices, Vol. 48, No. 10, 01.10.2001, p. 2317-2322.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Numerical confirmation of inelastic trap-assisted tunneling (ITAT) as SILC mechanism
AU - Kang, Ting Kuo
AU - Chen, Ming Jer
AU - Liu, Chuan Hsi
AU - Chang, Yih J.
AU - Fan, Shou Kong
PY - 2001/10/1
Y1 - 2001/10/1
N2 - This paper presents a quite comprehensive procedure covering both the stress-induced leakage current (SILC) and oxide breakdown, achieved by balancing systematically the modeling and experimental works. The underlying model as quoted in the literature features three key parameters: the tunneling relaxation time τ, the neutral electron trap density Nt, and the trap energy level Et. First of all, 7-nm thick oxide MOS devices with wide range oxide areas are throughly characterized in terms of the optically induced trap filling, the charge-to-breakdown statistics, the gate voltage developments with the time, and the SILC I-V. The former three are involved together with a percolation oxide breakdown model to build Nt explicitly as function of the stress electron fluence. Then the overall tunneling probability is calculated with which a best fitting to SILC I-V furnishes τ of 4.0 × 10-13 s and Et of 3.4 eV. The extracted τ is found to match exactly that extrapolated from existing data. Such striking consistencies thereby provide evidence that inelastic trap-assisted tunneling (ITAT) is indeed the SILC mechanism. Differences and similarities of the involved physical parameters between different studies are compared as well.
AB - This paper presents a quite comprehensive procedure covering both the stress-induced leakage current (SILC) and oxide breakdown, achieved by balancing systematically the modeling and experimental works. The underlying model as quoted in the literature features three key parameters: the tunneling relaxation time τ, the neutral electron trap density Nt, and the trap energy level Et. First of all, 7-nm thick oxide MOS devices with wide range oxide areas are throughly characterized in terms of the optically induced trap filling, the charge-to-breakdown statistics, the gate voltage developments with the time, and the SILC I-V. The former three are involved together with a percolation oxide breakdown model to build Nt explicitly as function of the stress electron fluence. Then the overall tunneling probability is calculated with which a best fitting to SILC I-V furnishes τ of 4.0 × 10-13 s and Et of 3.4 eV. The extracted τ is found to match exactly that extrapolated from existing data. Such striking consistencies thereby provide evidence that inelastic trap-assisted tunneling (ITAT) is indeed the SILC mechanism. Differences and similarities of the involved physical parameters between different studies are compared as well.
KW - Flash
KW - Gated-diode
KW - Inelastic tunneling
KW - MOSFET
KW - Oxide breakdown
KW - Percolation
KW - SILC
KW - Stress-induced leakage current
KW - Trap-assisted tunneling
UR - http://www.scopus.com/inward/record.url?scp=0035472026&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0035472026&partnerID=8YFLogxK
U2 - 10.1109/16.954471
DO - 10.1109/16.954471
M3 - Article
AN - SCOPUS:0035472026
VL - 48
SP - 2317
EP - 2322
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
SN - 0018-9383
IS - 10
ER -