Negative bias temperature instability (NBTI) in deep sub-micron p⁺-gate pMOSFETs

The device degradation, characterized by threshold voltage shift (ΔV_th), in deep sub-micron p⁺ polysilicon gate pMOSFETs due to negative bias temperature instability (NBTI) stress is studied. It is found that the negative threshold voltage shift tends to saturate with stress time. Both hydrogen ions and neutral atoms are believed to contribute to the generation of interface states. The I-V characteristics are compared before and after stresses and it shows that the interface degradation is symmetrical for S/D. In this work, a simple physical model is proposed to qualitatively explain the time evolution of the negative threshold voltage shift ΔV_th. This saturation implies continued formation of oxide-trapped holes and the accumulation of positive fixed oxide charges, inhibiting further transport of hydrogen ions and resulting in a gradual decrease in interface trap formation. Moreover, the activation energy E_A and field-acceleration parameter are also extracted to establish a general phenomenological model to predict the device lifetime of pMOSFETs characterized by threshold voltage shift.