Negative bias temperature instability (NBTI) in deep sub-micron p+-gate pMOSFETs

Y. F. Chen*, M. H. Lin, C. H. Chou, W. C. Chang, S. C. Huang, Y. J. Chang, K. Y. Fu, M. T. Lee, C. H. Liu, S. K. Fan

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

21 Citations (Scopus)


The device degradation, characterized by threshold voltage shift (ΔVth), in deep sub-micron p+ polysilicon gate pMOSFETs due to negative bias temperature instability (NBTI) stress is studied. It is found that the negative threshold voltage shift tends to saturate with stress time. Both hydrogen ions and neutral atoms are believed to contribute to the generation of interface states. The I-V characteristics are compared before and after stresses and it shows that the interface degradation is symmetrical for S/D. In this work, a simple physical model is proposed to qualitatively explain the time evolution of the negative threshold voltage shift ΔVth. This saturation implies continued formation of oxide-trapped holes and the accumulation of positive fixed oxide charges, inhibiting further transport of hydrogen ions and resulting in a gradual decrease in interface trap formation. Moreover, the activation energy EA and field-acceleration parameter are also extracted to establish a general phenomenological model to predict the device lifetime of pMOSFETs characterized by threshold voltage shift.

Original languageEnglish
Number of pages4
Publication statusPublished - 2000
Externally publishedYes
Event2000 IEEE International Integrated Reliability Workshop - Lake Tahoe, CA, USA
Duration: 2000 Oct 232000 Oct 26


Other2000 IEEE International Integrated Reliability Workshop
CityLake Tahoe, CA, USA

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Industrial and Manufacturing Engineering


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