@inproceedings{73da6401bb234e7bb96d224b6bdd9a77,
title = "NBTI mechanism explored on the back gate bias for pMOSFETs",
abstract = "Negative bias temperature instability had been getting more attention with the scaling down of MOS transistor, accompanied by the thinning of gate oxide. In our experiment of 0.15μm dual gate CMOS process, it is shown that surface hole concentration will have much impact on NBTI by means of Vsb application, no matter for devices of 2.6-nm or 6.5-nm oxide thickness. The NBTI enhancement at high Vsb is believed to be caused by the substrate hot hole injection, which leads to more interface state and positive charge generation, and thus makes NBTI worse. On the other hand, we expect better NBTI results under low gate electric field with Vsb applied, due to reduction of surface hole from Vsb.",
keywords = "Computer hacking, Degradation, Hot carriers, MOSFETs, Niobium compounds, Stress, Substrate hot electron injection, Temperature, Threshold voltage, Titanium compounds",
author = "Chen, {M. G.} and Li, {J. S.} and C. Jiang and Liu, {C. H.} and Su, {K. C.} and Chang, {Y. H.}",
note = "Publisher Copyright: {\textcopyright} 2003 IEEE.; 2003 IEEE International Integrated Reliability Workshop, IRW 2003 ; Conference date: 20-10-2003 Through 23-10-2003",
year = "2003",
doi = "10.1109/IRWS.2003.1283319",
language = "English",
series = "IEEE International Integrated Reliability Workshop Final Report",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "131--132",
booktitle = "2003 IEEE International Integrated Reliability Workshop Final Report, IRW 2003",
}