Multi-bit delta-sigma modulator using a modified DWA algorithm

Chien Hung Kuo; Tzu Chien Hsueh; Shen Iuan Liu

doi:10.1023/A:1020769913779

Multi-bit delta-sigma modulator using a modified DWA algorithm

Chien Hung Kuo, Tzu Chien Hsueh, Shen Iuan Liu

Research output: Contribution to journal › Article › peer-review

Abstract

A four pointer data weighted averaging (FPDWA) algorithm is presented to reduce the nonlinearity of the feedback multi-bit digital-to-analog converter (DAC) for delta-sigma modulators. By utilizing the proposed algorithm, the noise power caused by element mismatch can be reduced. A nine-level second-order delta-sigma modulator has been implemented in a double-poly double-metal 0.35 μm CMOS process. Experimental results indicate the peak SNDR reaches 86.59 dB within bandwidth of 22 kHz. The maximum input amplitude is -7 dB below the full scale with 10-kHz input frequency, the sampling frequency is 5 MHz, and the OSR is around 113. The power consumption is 6.27 mW for a power supply of 3.3 V.

Original language	English
Pages (from-to)	289-300
Number of pages	12
Journal	Analog Integrated Circuits and Signal Processing
Volume	33
Issue number	3
DOIs	https://doi.org/10.1023/A:1020769913779
Publication status	Published - 2002 Dec
Externally published	Yes

ASJC Scopus subject areas

Signal Processing
Hardware and Architecture
Surfaces, Coatings and Films

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title = "Multi-bit delta-sigma modulator using a modified DWA algorithm",

abstract = "A four pointer data weighted averaging (FPDWA) algorithm is presented to reduce the nonlinearity of the feedback multi-bit digital-to-analog converter (DAC) for delta-sigma modulators. By utilizing the proposed algorithm, the noise power caused by element mismatch can be reduced. A nine-level second-order delta-sigma modulator has been implemented in a double-poly double-metal 0.35 μm CMOS process. Experimental results indicate the peak SNDR reaches 86.59 dB within bandwidth of 22 kHz. The maximum input amplitude is -7 dB below the full scale with 10-kHz input frequency, the sampling frequency is 5 MHz, and the OSR is around 113. The power consumption is 6.27 mW for a power supply of 3.3 V.",

author = "Kuo, {Chien Hung} and Hsueh, {Tzu Chien} and Liu, {Shen Iuan}",

year = "2002",

month = dec,

doi = "10.1023/A:1020769913779",

language = "English",

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T1 - Multi-bit delta-sigma modulator using a modified DWA algorithm

AU - Kuo, Chien Hung

AU - Hsueh, Tzu Chien

AU - Liu, Shen Iuan

PY - 2002/12

Y1 - 2002/12

N2 - A four pointer data weighted averaging (FPDWA) algorithm is presented to reduce the nonlinearity of the feedback multi-bit digital-to-analog converter (DAC) for delta-sigma modulators. By utilizing the proposed algorithm, the noise power caused by element mismatch can be reduced. A nine-level second-order delta-sigma modulator has been implemented in a double-poly double-metal 0.35 μm CMOS process. Experimental results indicate the peak SNDR reaches 86.59 dB within bandwidth of 22 kHz. The maximum input amplitude is -7 dB below the full scale with 10-kHz input frequency, the sampling frequency is 5 MHz, and the OSR is around 113. The power consumption is 6.27 mW for a power supply of 3.3 V.

AB - A four pointer data weighted averaging (FPDWA) algorithm is presented to reduce the nonlinearity of the feedback multi-bit digital-to-analog converter (DAC) for delta-sigma modulators. By utilizing the proposed algorithm, the noise power caused by element mismatch can be reduced. A nine-level second-order delta-sigma modulator has been implemented in a double-poly double-metal 0.35 μm CMOS process. Experimental results indicate the peak SNDR reaches 86.59 dB within bandwidth of 22 kHz. The maximum input amplitude is -7 dB below the full scale with 10-kHz input frequency, the sampling frequency is 5 MHz, and the OSR is around 113. The power consumption is 6.27 mW for a power supply of 3.3 V.

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Multi-bit delta-sigma modulator using a modified DWA algorithm

Abstract

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