Multi-bit delta-sigma modulator using a modified DWA algorithm

Chien Hung Kuo, Tzu Chien Hsueh, Shen Iuan Liu

Research output: Contribution to journalArticle

Abstract

A four pointer data weighted averaging (FPDWA) algorithm is presented to reduce the nonlinearity of the feedback multi-bit digital-to-analog converter (DAC) for delta-sigma modulators. By utilizing the proposed algorithm, the noise power caused by element mismatch can be reduced. A nine-level second-order delta-sigma modulator has been implemented in a double-poly double-metal 0.35 μm CMOS process. Experimental results indicate the peak SNDR reaches 86.59 dB within bandwidth of 22 kHz. The maximum input amplitude is -7 dB below the full scale with 10-kHz input frequency, the sampling frequency is 5 MHz, and the OSR is around 113. The power consumption is 6.27 mW for a power supply of 3.3 V.

Original languageEnglish
Pages (from-to)289-300
Number of pages12
JournalAnalog Integrated Circuits and Signal Processing
Volume33
Issue number3
DOIs
Publication statusPublished - 2002 Dec

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Modulators
Digital to analog conversion
Electric power utilization
Metals
Sampling
Feedback
Bandwidth

ASJC Scopus subject areas

  • Signal Processing
  • Hardware and Architecture
  • Surfaces, Coatings and Films

Cite this

Multi-bit delta-sigma modulator using a modified DWA algorithm. / Kuo, Chien Hung; Hsueh, Tzu Chien; Liu, Shen Iuan.

In: Analog Integrated Circuits and Signal Processing, Vol. 33, No. 3, 12.2002, p. 289-300.

Research output: Contribution to journalArticle

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