Modeling of the parasitical capacitance effect in LCD panel and corresponding elimination strategy

Chang Hua Lin; Tsung You Hung; Chien Ming Wang; Kai Jun Pai

doi:10.1109/PEDS.2007.4487926

Modeling of the parasitical capacitance effect in LCD panel and corresponding elimination strategy

Chang Hua Lin^*, Tsung You Hung, Chien Ming Wang, Kai Jun Pai

^*Corresponding author for this work

Undergraduate Program of Vehicle and Energy Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A mathematical model of parasitical capacitance in LCD panel is conducted to explore the influence of leakage current effect on electric characteristics. First, a class D resonant backlight inverter is employed to act as the main circuit. Next, the phase angle variations caused by the parasitic capacitances is considered as a reference parameter in the proposed control strategy. By using the primary-side control and incorporating the DPLL technique to form a feedback mechanism to track the optimal operating frequency. And then the influence of parasitic capacitance can be reduced so as to eliminate the leakage current effect, hence, the system efficiency and stability will be improved. Complete mathematical analysis and design considerations are detailed. Experimental results agree with the theoretical predictions.

Original language	English
Title of host publication	7th International Conference on Power Electronics and Drive Systems, PEDS 2007
Pages	1618-1623
Number of pages	6
DOIs	https://doi.org/10.1109/PEDS.2007.4487926
Publication status	Published - 2007
Event	7th International Conference on Power Electronics and Drive Systems, PEDS 2007 - Bangkok, Thailand Duration: 2007 Nov 27 → 2007 Nov 30

Publication series

Name	Proceedings of the International Conference on Power Electronics and Drive Systems

Conference

Conference	7th International Conference on Power Electronics and Drive Systems, PEDS 2007
Country/Territory	Thailand
City	Bangkok
Period	2007/11/27 → 2007/11/30

Keywords

Backlight inverter
DPLL
Leakage current effect
Parasitical capacitance

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/PEDS.2007.4487926

Cite this

Lin, C. H., Hung, T. Y., Wang, C. M., & Pai, K. J. (2007). Modeling of the parasitical capacitance effect in LCD panel and corresponding elimination strategy. In 7th International Conference on Power Electronics and Drive Systems, PEDS 2007 (pp. 1618-1623). Article 4487926 (Proceedings of the International Conference on Power Electronics and Drive Systems). https://doi.org/10.1109/PEDS.2007.4487926

Modeling of the parasitical capacitance effect in LCD panel and corresponding elimination strategy. / Lin, Chang Hua; Hung, Tsung You; Wang, Chien Ming et al.
7th International Conference on Power Electronics and Drive Systems, PEDS 2007. 2007. p. 1618-1623 4487926 (Proceedings of the International Conference on Power Electronics and Drive Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Lin, CH, Hung, TY, Wang, CM & Pai, KJ 2007, Modeling of the parasitical capacitance effect in LCD panel and corresponding elimination strategy. in 7th International Conference on Power Electronics and Drive Systems, PEDS 2007., 4487926, Proceedings of the International Conference on Power Electronics and Drive Systems, pp. 1618-1623, 7th International Conference on Power Electronics and Drive Systems, PEDS 2007, Bangkok, Thailand, 2007/11/27. https://doi.org/10.1109/PEDS.2007.4487926

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title = "Modeling of the parasitical capacitance effect in LCD panel and corresponding elimination strategy",

abstract = "A mathematical model of parasitical capacitance in LCD panel is conducted to explore the influence of leakage current effect on electric characteristics. First, a class D resonant backlight inverter is employed to act as the main circuit. Next, the phase angle variations caused by the parasitic capacitances is considered as a reference parameter in the proposed control strategy. By using the primary-side control and incorporating the DPLL technique to form a feedback mechanism to track the optimal operating frequency. And then the influence of parasitic capacitance can be reduced so as to eliminate the leakage current effect, hence, the system efficiency and stability will be improved. Complete mathematical analysis and design considerations are detailed. Experimental results agree with the theoretical predictions.",

keywords = "Backlight inverter, DPLL, Leakage current effect, Parasitical capacitance",

author = "Lin, {Chang Hua} and Hung, {Tsung You} and Wang, {Chien Ming} and Pai, {Kai Jun}",

year = "2007",

doi = "10.1109/PEDS.2007.4487926",

language = "English",

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series = "Proceedings of the International Conference on Power Electronics and Drive Systems",

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T1 - Modeling of the parasitical capacitance effect in LCD panel and corresponding elimination strategy

AU - Lin, Chang Hua

AU - Hung, Tsung You

AU - Wang, Chien Ming

AU - Pai, Kai Jun

PY - 2007

Y1 - 2007

N2 - A mathematical model of parasitical capacitance in LCD panel is conducted to explore the influence of leakage current effect on electric characteristics. First, a class D resonant backlight inverter is employed to act as the main circuit. Next, the phase angle variations caused by the parasitic capacitances is considered as a reference parameter in the proposed control strategy. By using the primary-side control and incorporating the DPLL technique to form a feedback mechanism to track the optimal operating frequency. And then the influence of parasitic capacitance can be reduced so as to eliminate the leakage current effect, hence, the system efficiency and stability will be improved. Complete mathematical analysis and design considerations are detailed. Experimental results agree with the theoretical predictions.

AB - A mathematical model of parasitical capacitance in LCD panel is conducted to explore the influence of leakage current effect on electric characteristics. First, a class D resonant backlight inverter is employed to act as the main circuit. Next, the phase angle variations caused by the parasitic capacitances is considered as a reference parameter in the proposed control strategy. By using the primary-side control and incorporating the DPLL technique to form a feedback mechanism to track the optimal operating frequency. And then the influence of parasitic capacitance can be reduced so as to eliminate the leakage current effect, hence, the system efficiency and stability will be improved. Complete mathematical analysis and design considerations are detailed. Experimental results agree with the theoretical predictions.

KW - Backlight inverter

KW - DPLL

KW - Leakage current effect

KW - Parasitical capacitance

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Modeling of the parasitical capacitance effect in LCD panel and corresponding elimination strategy

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

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