Metal-gate/high-κ CMOS scaling from Si to Ge at small EOT

Albert Chin; W. B. Chen; B. S. Shie; K. C. Hsu; P. C. Chen; C. H. Cheng; C. C. Chi; Y. H. Wu; K. S. Chaing-Liaoc; S. J. Wang; C. H. Kuan; F. S. Yeh

doi:10.1109/ICSICT.2010.5667443

Metal-gate/high-κ CMOS scaling from Si to Ge at small EOT

Albert Chin^*
, W. B. Chen
, B. S. Shie
, K. C. Hsu
, P. C. Chen
, C. H. Cheng
, C. C. Chi
, Y. H. Wu
, K. S. Chaing-Liaoc
, S. J. Wang
, C. H. Kuan
, F. S. Yeh

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

Continuously down-scaling EOT and improving mobility are required for CMOS device. Small 0.6∼1 nm EOT and low V_t of ∼0.15 V are achieved in CMOS by using higher κ gate dielectric and novel process. The ultimate EOT scaling is limited by the inserted ultra-thin SiON interfacial layer in high-κ/Si to reduce the mobility degradation. Further mobility improvement is obtained by using Ge channel MOSFET that has 2.5X better high-field hole effective mobility than the SiO₂/Si universal mobility at an E _eff of 1 MV/cm.

Original language	English
Title of host publication	ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings
Pages	836-839
Number of pages	4
DOIs	https://doi.org/10.1109/ICSICT.2010.5667443
Publication status	Published - 2010
Externally published	Yes
Event	2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology - Shanghai, China Duration: 2010 Nov 1 → 2010 Nov 4

Publication series

Name	ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings

Other

Other	2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology
Country/Territory	China
City	Shanghai
Period	2010/11/01 → 2010/11/04

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ICSICT.2010.5667443

Cite this

Chin, A., Chen, W. B., Shie, B. S., Hsu, K. C., Chen, P. C., Cheng, C. H., Chi, C. C., Wu, Y. H., Chaing-Liaoc, K. S., Wang, S. J., Kuan, C. H., & Yeh, F. S. (2010). Metal-gate/high-κ CMOS scaling from Si to Ge at small EOT. In ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings (pp. 836-839). Article 5667443 (ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings). https://doi.org/10.1109/ICSICT.2010.5667443

Metal-gate/high-κ CMOS scaling from Si to Ge at small EOT. / Chin, Albert; Chen, W. B.; Shie, B. S. et al.
ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2010. p. 836-839 5667443 (ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Chin, A, Chen, WB, Shie, BS, Hsu, KC, Chen, PC, Cheng, CH, Chi, CC, Wu, YH, Chaing-Liaoc, KS, Wang, SJ, Kuan, CH & Yeh, FS 2010, Metal-gate/high-κ CMOS scaling from Si to Ge at small EOT. in ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings., 5667443, ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings, pp. 836-839, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Shanghai, China, 2010/11/01. https://doi.org/10.1109/ICSICT.2010.5667443

Chin A, Chen WB, Shie BS, Hsu KC, Chen PC, Cheng CH et al. Metal-gate/high-κ CMOS scaling from Si to Ge at small EOT. In ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2010. p. 836-839. 5667443. (ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings). doi: 10.1109/ICSICT.2010.5667443

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title = "Metal-gate/high-κ CMOS scaling from Si to Ge at small EOT",

abstract = "Continuously down-scaling EOT and improving mobility are required for CMOS device. Small 0.6∼1 nm EOT and low Vt of ∼0.15 V are achieved in CMOS by using higher κ gate dielectric and novel process. The ultimate EOT scaling is limited by the inserted ultra-thin SiON interfacial layer in high-κ/Si to reduce the mobility degradation. Further mobility improvement is obtained by using Ge channel MOSFET that has 2.5X better high-field hole effective mobility than the SiO2/Si universal mobility at an E eff of 1 MV/cm.",

author = "Albert Chin and Chen, \{W. B.\} and Shie, \{B. S.\} and Hsu, \{K. C.\} and Chen, \{P. C.\} and Cheng, \{C. H.\} and Chi, \{C. C.\} and Wu, \{Y. H.\} and Chaing-Liaoc, \{K. S.\} and Wang, \{S. J.\} and Kuan, \{C. H.\} and Yeh, \{F. S.\}",

year = "2010",

doi = "10.1109/ICSICT.2010.5667443",

language = "English",

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series = "ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings",

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AU - Chin, Albert

AU - Chen, W. B.

AU - Shie, B. S.

AU - Hsu, K. C.

AU - Chen, P. C.

AU - Cheng, C. H.

AU - Chi, C. C.

AU - Wu, Y. H.

AU - Chaing-Liaoc, K. S.

AU - Wang, S. J.

AU - Kuan, C. H.

AU - Yeh, F. S.

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AB - Continuously down-scaling EOT and improving mobility are required for CMOS device. Small 0.6∼1 nm EOT and low Vt of ∼0.15 V are achieved in CMOS by using higher κ gate dielectric and novel process. The ultimate EOT scaling is limited by the inserted ultra-thin SiON interfacial layer in high-κ/Si to reduce the mobility degradation. Further mobility improvement is obtained by using Ge channel MOSFET that has 2.5X better high-field hole effective mobility than the SiO2/Si universal mobility at an E eff of 1 MV/cm.

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ER -

Metal-gate/high-κ CMOS scaling from Si to Ge at small EOT

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