Metal-gate/high-κ CMOS scaling from Si to Ge at small EOT

Albert Chin, W. B. Chen, B. S. Shie, K. C. Hsu, P. C. Chen, Chun-Hu Cheng, C. C. Chi, Y. H. Wu, K. S. Chaing-Liaoc, S. J. Wang, C. H. Kuan, F. S. Yeh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Continuously down-scaling EOT and improving mobility are required for CMOS device. Small 0.6∼1 nm EOT and low Vt of ∼0.15 V are achieved in CMOS by using higher κ gate dielectric and novel process. The ultimate EOT scaling is limited by the inserted ultra-thin SiON interfacial layer in high-κ/Si to reduce the mobility degradation. Further mobility improvement is obtained by using Ge channel MOSFET that has 2.5X better high-field hole effective mobility than the SiO2/Si universal mobility at an E eff of 1 MV/cm.

Original languageEnglish
Title of host publicationICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings
Pages836-839
Number of pages4
DOIs
Publication statusPublished - 2010 Dec 1
Event2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology - Shanghai, China
Duration: 2010 Nov 12010 Nov 4

Publication series

NameICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings

Other

Other2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology
CountryChina
CityShanghai
Period10/11/110/11/4

Fingerprint

Hole mobility
Gate dielectrics
Degradation
Metals

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Chin, A., Chen, W. B., Shie, B. S., Hsu, K. C., Chen, P. C., Cheng, C-H., ... Yeh, F. S. (2010). Metal-gate/high-κ CMOS scaling from Si to Ge at small EOT. In ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings (pp. 836-839). [5667443] (ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings). https://doi.org/10.1109/ICSICT.2010.5667443

Metal-gate/high-κ CMOS scaling from Si to Ge at small EOT. / Chin, Albert; Chen, W. B.; Shie, B. S.; Hsu, K. C.; Chen, P. C.; Cheng, Chun-Hu; Chi, C. C.; Wu, Y. H.; Chaing-Liaoc, K. S.; Wang, S. J.; Kuan, C. H.; Yeh, F. S.

ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2010. p. 836-839 5667443 (ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Chin, A, Chen, WB, Shie, BS, Hsu, KC, Chen, PC, Cheng, C-H, Chi, CC, Wu, YH, Chaing-Liaoc, KS, Wang, SJ, Kuan, CH & Yeh, FS 2010, Metal-gate/high-κ CMOS scaling from Si to Ge at small EOT. in ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings., 5667443, ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings, pp. 836-839, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Shanghai, China, 10/11/1. https://doi.org/10.1109/ICSICT.2010.5667443
Chin A, Chen WB, Shie BS, Hsu KC, Chen PC, Cheng C-H et al. Metal-gate/high-κ CMOS scaling from Si to Ge at small EOT. In ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2010. p. 836-839. 5667443. (ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings). https://doi.org/10.1109/ICSICT.2010.5667443
Chin, Albert ; Chen, W. B. ; Shie, B. S. ; Hsu, K. C. ; Chen, P. C. ; Cheng, Chun-Hu ; Chi, C. C. ; Wu, Y. H. ; Chaing-Liaoc, K. S. ; Wang, S. J. ; Kuan, C. H. ; Yeh, F. S. / Metal-gate/high-κ CMOS scaling from Si to Ge at small EOT. ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2010. pp. 836-839 (ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings).
@inproceedings{dd410fde79cb4b2295b6869281540f82,
title = "Metal-gate/high-κ CMOS scaling from Si to Ge at small EOT",
abstract = "Continuously down-scaling EOT and improving mobility are required for CMOS device. Small 0.6∼1 nm EOT and low Vt of ∼0.15 V are achieved in CMOS by using higher κ gate dielectric and novel process. The ultimate EOT scaling is limited by the inserted ultra-thin SiON interfacial layer in high-κ/Si to reduce the mobility degradation. Further mobility improvement is obtained by using Ge channel MOSFET that has 2.5X better high-field hole effective mobility than the SiO2/Si universal mobility at an E eff of 1 MV/cm.",
author = "Albert Chin and Chen, {W. B.} and Shie, {B. S.} and Hsu, {K. C.} and Chen, {P. C.} and Chun-Hu Cheng and Chi, {C. C.} and Wu, {Y. H.} and Chaing-Liaoc, {K. S.} and Wang, {S. J.} and Kuan, {C. H.} and Yeh, {F. S.}",
year = "2010",
month = "12",
day = "1",
doi = "10.1109/ICSICT.2010.5667443",
language = "English",
isbn = "9781424457984",
series = "ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings",
pages = "836--839",
booktitle = "ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings",

}

TY - GEN

T1 - Metal-gate/high-κ CMOS scaling from Si to Ge at small EOT

AU - Chin, Albert

AU - Chen, W. B.

AU - Shie, B. S.

AU - Hsu, K. C.

AU - Chen, P. C.

AU - Cheng, Chun-Hu

AU - Chi, C. C.

AU - Wu, Y. H.

AU - Chaing-Liaoc, K. S.

AU - Wang, S. J.

AU - Kuan, C. H.

AU - Yeh, F. S.

PY - 2010/12/1

Y1 - 2010/12/1

N2 - Continuously down-scaling EOT and improving mobility are required for CMOS device. Small 0.6∼1 nm EOT and low Vt of ∼0.15 V are achieved in CMOS by using higher κ gate dielectric and novel process. The ultimate EOT scaling is limited by the inserted ultra-thin SiON interfacial layer in high-κ/Si to reduce the mobility degradation. Further mobility improvement is obtained by using Ge channel MOSFET that has 2.5X better high-field hole effective mobility than the SiO2/Si universal mobility at an E eff of 1 MV/cm.

AB - Continuously down-scaling EOT and improving mobility are required for CMOS device. Small 0.6∼1 nm EOT and low Vt of ∼0.15 V are achieved in CMOS by using higher κ gate dielectric and novel process. The ultimate EOT scaling is limited by the inserted ultra-thin SiON interfacial layer in high-κ/Si to reduce the mobility degradation. Further mobility improvement is obtained by using Ge channel MOSFET that has 2.5X better high-field hole effective mobility than the SiO2/Si universal mobility at an E eff of 1 MV/cm.

UR - http://www.scopus.com/inward/record.url?scp=78751530581&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=78751530581&partnerID=8YFLogxK

U2 - 10.1109/ICSICT.2010.5667443

DO - 10.1109/ICSICT.2010.5667443

M3 - Conference contribution

AN - SCOPUS:78751530581

SN - 9781424457984

T3 - ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings

SP - 836

EP - 839

BT - ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings

ER -