Abstract
The physical mechanism responsible for negative bias temperature instability (NBTI), which is basic to the minimization of this degradation mode, is investigated, and an analytical model is developed accordingly. Experiments with 1.7 nm to 3.3 nm gate dielectrics fabricated by different processes demonstrate the capability of the proposed model.
| Original language | English |
|---|---|
| Pages (from-to) | 2423-2425 |
| Number of pages | 3 |
| Journal | Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers |
| Volume | 41 |
| Issue number | 4 B |
| DOIs | |
| Publication status | Published - 2002 Apr |
| Externally published | Yes |
Keywords
- Device physics
- Gate oxide reliability
- NBTI
ASJC Scopus subject areas
- General Engineering
- General Physics and Astronomy
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